From 8e28947dacb52352807fed71d70355a18bf416c5 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 8 Feb 2018 14:38:35 +0800 Subject: [PATCH] MLK-17566: ASoC: fsl_sai: fix register definition The register definition is not completed for SAI support 8 transmit data register and 8 receive data register. Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta --- sound/soc/fsl/fsl_sai.c | 24 ++++++++++++++++++++++++ sound/soc/fsl/fsl_sai.h | 12 ++++++++++++ 2 files changed, 36 insertions(+) --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -964,6 +964,12 @@ static struct reg_default fsl_sai_v3_reg {FSL_SAI_TCR5(8), 0}, {FSL_SAI_TDR0, 0}, {FSL_SAI_TDR1, 0}, + {FSL_SAI_TDR2, 0}, + {FSL_SAI_TDR3, 0}, + {FSL_SAI_TDR4, 0}, + {FSL_SAI_TDR5, 0}, + {FSL_SAI_TDR6, 0}, + {FSL_SAI_TDR7, 0}, {FSL_SAI_TMR, 0}, {FSL_SAI_RCR1(8), 0}, {FSL_SAI_RCR2(8), 0}, @@ -996,6 +1002,12 @@ static bool fsl_sai_readable_reg(struct case FSL_SAI_TMR: case FSL_SAI_RDR0: case FSL_SAI_RDR1: + case FSL_SAI_RDR2: + case FSL_SAI_RDR3: + case FSL_SAI_RDR4: + case FSL_SAI_RDR5: + case FSL_SAI_RDR6: + case FSL_SAI_RDR7: case FSL_SAI_RFR0: case FSL_SAI_RFR1: case FSL_SAI_RFR2: @@ -1038,6 +1050,12 @@ static bool fsl_sai_volatile_reg(struct case FSL_SAI_RFR7: case FSL_SAI_RDR0: case FSL_SAI_RDR1: + case FSL_SAI_RDR2: + case FSL_SAI_RDR3: + case FSL_SAI_RDR4: + case FSL_SAI_RDR5: + case FSL_SAI_RDR6: + case FSL_SAI_RDR7: return true; default: return false; @@ -1058,6 +1076,12 @@ static bool fsl_sai_writeable_reg(struct switch (reg) { case FSL_SAI_TDR0: case FSL_SAI_TDR1: + case FSL_SAI_TDR2: + case FSL_SAI_TDR3: + case FSL_SAI_TDR4: + case FSL_SAI_TDR5: + case FSL_SAI_TDR6: + case FSL_SAI_TDR7: case FSL_SAI_TMR: case FSL_SAI_RMR: return true; --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -25,6 +25,12 @@ #define FSL_SAI_TCR5(offset) (0x14 + offset) /* SAI Transmit Configuration 5 */ #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data */ #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data */ +#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data */ +#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data */ +#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data */ +#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data */ +#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data */ +#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data */ #define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO */ #define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO */ #define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO */ @@ -43,6 +49,12 @@ #define FSL_SAI_RCR5(offset) (0x94 + offset) /* SAI Receive Configuration 5 */ #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data */ #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data */ +#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data */ +#define FSL_SAI_RDR3 0xac /* SAI Receive Data */ +#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data */ +#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data */ +#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data */ +#define FSL_SAI_RDR7 0xbc /* SAI Receive Data */ #define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO */ #define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO */ #define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO */