From 04493d5f2adffe3473941a860ef77bfd5ee05ed3 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 31 Aug 2023 11:05:06 +0800 Subject: [PATCH] Revert "ASoC: fsl_sai: Add new added registers and new bit definition" This reverts commit ef9cae4a6c8d4f8822540bed20c2d1eb37722408. --- sound/soc/fsl/fsl_sai.c | 23 ---------------- sound/soc/fsl/fsl_sai.h | 59 ----------------------------------------- 2 files changed, 82 deletions(-) --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -810,8 +810,6 @@ static struct reg_default fsl_sai_reg_de {FSL_SAI_RCR4(8), 0}, {FSL_SAI_RCR5(8), 0}, {FSL_SAI_RMR, 0}, - {FSL_SAI_MCTL, 0}, - {FSL_SAI_MDIV, 0}, }; static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) @@ -852,18 +850,6 @@ static bool fsl_sai_readable_reg(struct case FSL_SAI_RFR6: case FSL_SAI_RFR7: case FSL_SAI_RMR: - case FSL_SAI_MCTL: - case FSL_SAI_MDIV: - case FSL_SAI_VERID: - case FSL_SAI_PARAM: - case FSL_SAI_TTCTN: - case FSL_SAI_RTCTN: - case FSL_SAI_TTCTL: - case FSL_SAI_TBCTN: - case FSL_SAI_TTCAP: - case FSL_SAI_RTCTL: - case FSL_SAI_RBCTN: - case FSL_SAI_RTCAP: return true; default: return false; @@ -878,10 +864,6 @@ static bool fsl_sai_volatile_reg(struct if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) return true; - /* Set VERID and PARAM be volatile for reading value in probe */ - if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) - return true; - switch (reg) { case FSL_SAI_TFR0: case FSL_SAI_TFR1: @@ -935,10 +917,6 @@ static bool fsl_sai_writeable_reg(struct case FSL_SAI_TDR7: case FSL_SAI_TMR: case FSL_SAI_RMR: - case FSL_SAI_MCTL: - case FSL_SAI_MDIV: - case FSL_SAI_TTCTL: - case FSL_SAI_RTCTL: return true; default: return false; @@ -987,7 +965,6 @@ static int fsl_sai_probe(struct platform if (sai->soc_data->reg_offset == 8) { fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; - fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; fsl_sai_regmap_config.num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); } --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -14,8 +14,6 @@ SNDRV_PCM_FMTBIT_S32_LE) /* SAI Register Map Register */ -#define FSL_SAI_VERID 0x00 /* SAI Version ID Register */ -#define FSL_SAI_PARAM 0x04 /* SAI Parameter Register */ #define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */ #define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */ #define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */ @@ -39,10 +37,6 @@ #define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */ #define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */ #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ -#define FSL_SAI_TTCTL 0x70 /* SAI Transmit Timestamp Control Register */ -#define FSL_SAI_TTCTN 0x74 /* SAI Transmit Timestamp Counter Register */ -#define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */ -#define FSL_SAI_TTCAP 0x7C /* SAI Transmit Timestamp Capture */ #define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */ #define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */ #define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */ @@ -66,13 +60,6 @@ #define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */ #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */ #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */ -#define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */ -#define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */ -#define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */ -#define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */ - -#define FSL_SAI_MCTL 0x100 /* SAI MCLK Control Register */ -#define FSL_SAI_MDIV 0x104 /* SAI MCLK Divide Register */ #define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs)) #define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs)) @@ -86,7 +73,6 @@ /* SAI Transmit/Receive Control Register */ #define FSL_SAI_CSR_TERE BIT(31) -#define FSL_SAI_CSR_SE BIT(30) #define FSL_SAI_CSR_FR BIT(25) #define FSL_SAI_CSR_SR BIT(24) #define FSL_SAI_CSR_xF_SHIFT 16 @@ -120,7 +106,6 @@ #define FSL_SAI_CR2_MSEL(ID) ((ID) << 26) #define FSL_SAI_CR2_BCP BIT(25) #define FSL_SAI_CR2_BCD_MSTR BIT(24) -#define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */ #define FSL_SAI_CR2_DIV_MASK 0xff /* SAI Transmit and Receive Configuration 3 Register */ @@ -130,13 +115,6 @@ #define FSL_SAI_CR3_WDFL_MASK 0x1f /* SAI Transmit and Receive Configuration 4 Register */ - -#define FSL_SAI_CR4_FCONT BIT(28) -#define FSL_SAI_CR4_FCOMB_SHIFT BIT(26) -#define FSL_SAI_CR4_FCOMB_SOFT BIT(27) -#define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26) -#define FSL_SAI_CR4_FPACK_8 (0x2 << 24) -#define FSL_SAI_CR4_FPACK_16 (0x3 << 24) #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) @@ -154,43 +132,6 @@ #define FSL_SAI_CR5_FBT(x) ((x) << 8) #define FSL_SAI_CR5_FBT_MASK (0x1f << 8) -/* SAI MCLK Control Register */ -#define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */ -#define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24) -#define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24) -#define FSL_SAI_MCTL_MSEL_BUS 0 -#define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24) -#define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25) -#define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25)) -#define FSL_SAI_MCTL_DIV_EN BIT(23) -#define FSL_SAI_MCTL_DIV_MASK 0xFF - -/* SAI VERID Register */ -#define FSL_SAI_VERID_MAJOR_SHIFT 24 -#define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24) -#define FSL_SAI_VERID_MINOR_SHIFT 16 -#define FSL_SAI_VERID_MINOR_MASK GENMASK(23, 16) -#define FSL_SAI_VERID_FEATURE_SHIFT 0 -#define FSL_SAI_VERID_FEATURE_MASK GENMASK(15, 0) -#define FSL_SAI_VERID_EFIFO_EN BIT(0) -#define FSL_SAI_VERID_TSTMP_EN BIT(1) - -/* SAI PARAM Register */ -#define FSL_SAI_PARAM_SPF_SHIFT 16 -#define FSL_SAI_PARAM_SPF_MASK GENMASK(19, 16) -#define FSL_SAI_PARAM_WPF_SHIFT 8 -#define FSL_SAI_PARAM_WPF_MASK GENMASK(11, 8) -#define FSL_SAI_PARAM_DLN_MASK GENMASK(3, 0) - -/* SAI MCLK Divide Register */ -#define FSL_SAI_MDIV_MASK 0xFFFFF - -/* SAI timestamp and bitcounter */ -#define FSL_SAI_xTCTL_TSEN BIT(0) -#define FSL_SAI_xTCTL_TSINC BIT(1) -#define FSL_SAI_xTCTL_RTSC BIT(8) -#define FSL_SAI_xTCTL_RBC BIT(9) - /* SAI type */ #define FSL_SAI_DMA BIT(0) #define FSL_SAI_USE_AC97 BIT(1)