From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001 From: hmz007 Date: Tue, 19 Nov 2019 14:21:51 +0800 Subject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node Signed-off-by: hmz007 --- .../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++ .../dts/rockchip/rk3328-nanopi-r2-common.dtsi | 85 ++++- include/dt-bindings/clock/rockchip-ddr.h | 63 ++++ include/dt-bindings/memory/rk3328-dram.h | 159 +++++++++ 4 files changed, 617 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi create mode 100644 include/dt-bindings/clock/rockchip-ddr.h create mode 100644 include/dt-bindings/memory/rk3328-dram.h --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts @@ -7,6 +7,7 @@ #include #include +#include "rk3328-dram-default-timing.dtsi" #include "rk3328.dtsi" / { @@ -115,6 +116,72 @@ regulator-max-microvolt = <5000000>; enable-active-high; }; + + dmc: dmc { + compatible = "rockchip,rk3328-dmc"; + devfreq-events = <&dfi>; + center-supply = <&vdd_log>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + auto-min-freq = <786000>; + auto-freq-en = <0>; + #cooling-cells = <2>; + status = "okay"; + + ddr_power_model: ddr_power_model { + compatible = "ddr_power_model"; + dynamic-power-coefficient = <120>; + static-power-coefficient = <200>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "soc-thermal"; + }; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "ddr_leakage"; + + opp-786000000 { + opp-hz = /bits/ 64 <786000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-798000000 { + opp-hz = /bits/ 64 <798000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <1100000>; + opp-microvolt-L0 = <1100000>; + opp-microvolt-L1 = <1075000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1175000>; + opp-microvolt-L0 = <1175000>; + opp-microvolt-L1 = <1150000>; + }; + }; }; &cpu0 { @@ -133,6 +200,10 @@ cpu-supply = <&vdd_arm>; }; +&dfi { + status = "okay"; +}; + &gmac2io { assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; @@ -198,6 +269,7 @@ regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <1075000>; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-ramp-delay = <12500>; @@ -212,6 +284,7 @@ regulator-name = "vdd_arm"; regulator-always-on; regulator-boot-on; + regulator-init-microvolt = <1225000>; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-ramp-delay = <12500>; --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -4,6 +4,7 @@ */ /dts-v1/; +#include "rk3328-dram-renegade-timing.dtsi" #include "rk3328.dtsi" / { @@ -105,6 +106,72 @@ default-state = "off"; }; }; + + dmc: dmc { + compatible = "rockchip,rk3328-dmc"; + devfreq-events = <&dfi>; + center-supply = <&vdd_logic>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + auto-min-freq = <786000>; + auto-freq-en = <0>; + #cooling-cells = <2>; + status = "okay"; + + ddr_power_model: ddr_power_model { + compatible = "ddr_power_model"; + dynamic-power-coefficient = <120>; + static-power-coefficient = <200>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "soc-thermal"; + }; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "ddr_leakage"; + + opp-786000000 { + opp-hz = /bits/ 64 <786000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <12000000>; + }; + opp-798000000 { + opp-hz = /bits/ 64 <798000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <12000000>; + }; + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <12000000>; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <1100000>; + opp-microvolt-L0 = <1100000>; + opp-microvolt-L1 = <12000000>; + }; + opp-1068000000 { + opp-hz = /bits/ 64 <1068000000>; + opp-microvolt = <1175000>; + opp-microvolt-L0 = <1175000>; + opp-microvolt-L1 = <12000000>; + }; + }; }; &cpu0 { @@ -123,6 +190,10 @@ cpu-supply = <&vdd_arm>; }; +&dfi { + status = "okay"; +}; + &emmc { bus-width = <8>; cap-mmc-highspeed; @@ -191,6 +262,7 @@ regulators { vdd_logic: DCDC_REG1 { regulator-name = "vdd_logic"; + regulator-init-microvolt = <1075000>; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-always-on; @@ -203,6 +275,7 @@ vdd_arm: DCDC_REG2 { regulator-name = "vdd_arm"; + regulator-init-microvolt = <1225000>; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; regulator-always-on;