From b3d0e4379011418250d367bbcb4058a891c2163c Mon Sep 17 00:00:00 2001 From: Sujuan Chen Date: Tue, 18 Jan 2022 16:16:53 +0800 Subject: [PATCH] mt7986:update ppe from mt7622 to mt7986 Signed-off-by: Sujuan Chen --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- drivers/net/ethernet/mediatek/mtk_ppe.c | 26 +++---- drivers/net/ethernet/mediatek/mtk_ppe.h | 71 +++++++++++-------- .../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +- drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 10 +++ 6 files changed, 67 insertions(+), 45 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index bf623ff..537416e 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -3730,6 +3730,7 @@ static const struct mtk_soc_data mt7986_data = { .required_clks = MT7986_CLKS_BITMAP, .required_pctl = false, .has_sram = true, + .offload_version = 2, }; static const struct mtk_soc_data mt7981_data = { diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 532efdc..14e2abf 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -98,7 +98,7 @@ #define MTK_GDMA_TCS_EN BIT(21) #define MTK_GDMA_UCS_EN BIT(20) #define MTK_GDMA_TO_PDMA 0x0 -#define MTK_GDMA_TO_PPE 0x4444 +#define MTK_GDMA_TO_PPE 0x3333 #define MTK_GDMA_DROP_ALL 0x7777 /* Unicast Filter MAC Address Register - Low */ diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c index ec7b6e6..d9837fc 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c @@ -111,7 +111,7 @@ static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e) hash = (hash >> 24) | ((hash & 0xffffff) << 8); hash ^= hv1 ^ hv2 ^ hv3; hash ^= hash >> 16; - hash <<= 1; + hash <<= 2; hash &= MTK_PPE_ENTRIES - 1; return hash; @@ -154,8 +154,7 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto, MTK_FOE_IB1_BIND_CACHE; entry->ib1 = val; - val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) | - FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) | + val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) | FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port); if (is_multicast_ether_addr(dest_mac)) @@ -335,14 +334,11 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry); u32 *ib2 = mtk_foe_entry_ib2(entry); - *ib2 &= ~MTK_FOE_IB2_PORT_MG; *ib2 |= MTK_FOE_IB2_WDMA_WINFO; - if (wdma_idx) - *ib2 |= MTK_FOE_IB2_WDMA_DEVIDX; + *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq); - l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) | - FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) | - FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq); + l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | + FIELD_PREP(MTK_FOE_WINFO_BSS, bss); return 0; } @@ -437,6 +433,7 @@ int mtk_ppe_start(struct mtk_ppe *ppe) MTK_PPE_TB_CFG_AGE_TCP | MTK_PPE_TB_CFG_AGE_UDP | MTK_PPE_TB_CFG_AGE_TCP_FIN | + MTK_PPE_TB_CFG_INFO_SEL | FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS, MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) | FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE, @@ -453,7 +450,9 @@ int mtk_ppe_start(struct mtk_ppe *ppe) mtk_ppe_cache_enable(ppe, true); - val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG | + val = MTK_PPE_MD_TOAP_BYP_CRSN0 | + MTK_PPE_MD_TOAP_BYP_CRSN1 | + MTK_PPE_MD_TOAP_BYP_CRSN2 | MTK_PPE_FLOW_CFG_IP4_UDP_FRAG | MTK_PPE_FLOW_CFG_IP6_3T_ROUTE | MTK_PPE_FLOW_CFG_IP6_5T_ROUTE | @@ -461,8 +460,8 @@ int mtk_ppe_start(struct mtk_ppe *ppe) MTK_PPE_FLOW_CFG_IP4_NAT | MTK_PPE_FLOW_CFG_IP4_NAPT | MTK_PPE_FLOW_CFG_IP4_DSLITE | - MTK_PPE_FLOW_CFG_L2_BRIDGE | - MTK_PPE_FLOW_CFG_IP4_NAT_FRAG; + MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY | + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG ; ppe_w32(ppe, MTK_PPE_FLOW_CFG, val); val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) | @@ -497,6 +496,9 @@ int mtk_ppe_start(struct mtk_ppe *ppe) ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); + ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); + return 0; } diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h index df8ccaf..0efd57e 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h @@ -7,7 +7,7 @@ #include #include -#define MTK_ETH_PPE_BASE 0xc00 +#define MTK_ETH_PPE_BASE 0x2000 #define MTK_PPE_ENTRIES_SHIFT 3 #define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT) @@ -15,20 +15,25 @@ #define MTK_PPE_WAIT_TIMEOUT_US 1000000 #define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) -#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) -#define MTK_FOE_IB1_UNBIND_PREBIND BIT(24) - -#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) -#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(15) -#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16) -#define MTK_FOE_IB1_BIND_PPPOE BIT(19) -#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(20) -#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(21) -#define MTK_FOE_IB1_BIND_CACHE BIT(22) -#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) -#define MTK_FOE_IB1_BIND_TTL BIT(24) - -#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25) +#define MTK_FOE_IB1_UNBIND_SRC_PORT GENMASK(11, 8) +#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(19, 12) +#define MTK_FOE_IB1_UNBIND_PREBIND BIT(22) +#define MTK_FOE_IB1_UNBIND_PACKET_TYPE GENMASK(27, 23) + +#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(7, 0) +#define MTK_FOE_IB1_BIND_SRC_PORT GENMASK(11, 8) +#define MTK_FOE_IB1_BIND_MC BIT(12) +#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(13) + +#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(16, 14) +#define MTK_FOE_IB1_BIND_PPPOE BIT(17) +#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(18) +#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(19) +#define MTK_FOE_IB1_BIND_CACHE BIT(20) +#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(21) +#define MTK_FOE_IB1_BIND_TTL BIT(22) + +#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 23) #define MTK_FOE_IB1_STATE GENMASK(29, 28) #define MTK_FOE_IB1_UDP BIT(30) #define MTK_FOE_IB1_STATIC BIT(31) @@ -43,24 +48,20 @@ enum { MTK_PPE_PKT_TYPE_IPV6_6RD = 7, }; -#define MTK_FOE_IB2_QID GENMASK(3, 0) -#define MTK_FOE_IB2_PSE_QOS BIT(4) -#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5) -#define MTK_FOE_IB2_MULTICAST BIT(8) - -#define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12) -#define MTK_FOE_IB2_WDMA_DEVIDX BIT(16) -#define MTK_FOE_IB2_WDMA_WINFO BIT(17) - -#define MTK_FOE_IB2_PORT_MG GENMASK(17, 12) - -#define MTK_FOE_IB2_PORT_AG GENMASK(23, 18) +#define MTK_FOE_IB2_QID GENMASK(6, 0) +#define MTK_FOE_IB2_PORT_MG BIT(7) +#define MTK_FOE_IB2_PSE_QOS BIT(8) +#define MTK_FOE_IB2_DEST_PORT GENMASK(12, 9) +#define MTK_FOE_IB2_MULTICAST BIT(13) +#define MTK_FOE_IB2_MIB_CNT BIT(15) +#define MTK_FOE_IB2_RX_IDX GENMASK(18, 17) +#define MTK_FOE_IB2_WDMA_WINFO BIT(19) +#define MTK_FOE_IB2_PORT_AG GENMASK(23, 20) #define MTK_FOE_IB2_DSCP GENMASK(31, 24) -#define MTK_FOE_VLAN2_WINFO_BSS GENMASK(5, 0) -#define MTK_FOE_VLAN2_WINFO_WCID GENMASK(13, 6) -#define MTK_FOE_VLAN2_WINFO_RING GENMASK(15, 14) +#define MTK_FOE_WINFO_BSS GENMASK(5, 0) +#define MTK_FOE_WINFO_WCID GENMASK(15, 6) enum { MTK_FOE_STATE_INVALID, @@ -82,6 +83,9 @@ struct mtk_foe_mac_info { u16 pppoe_id; u16 src_mac_lo; + + u16 minfo; + u16 winfo; }; struct mtk_foe_bridge { @@ -145,6 +149,11 @@ struct mtk_foe_ipv4_dslite { u32 ib2; struct mtk_foe_mac_info l2; + u32 new_sip; + u32 new_dip; + u16 new_dport; + u16 new_sport; + }; struct mtk_foe_ipv6 { @@ -202,7 +211,7 @@ struct mtk_foe_entry { struct mtk_foe_ipv4_dslite dslite; struct mtk_foe_ipv6 ipv6; struct mtk_foe_ipv6_6rd ipv6_6rd; - u32 data[19]; + u32 data[23]; }; }; diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c index f621a8d..1895b6c 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c @@ -156,7 +156,7 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, mtk_foe_entry_set_wdma(foe, path.mtk_wdma.wdma_idx, path.mtk_wdma.queue, path.mtk_wdma.bss, path.mtk_wdma.wcid); - mtk_foe_entry_set_pse_port(foe, 3); + mtk_foe_entry_set_pse_port(foe, 8); *wed_index = path.mtk_wdma.wdma_idx; return 0; default: diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h index 0c45ea0..6c06fba 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h @@ -21,6 +21,9 @@ #define MTK_PPE_GLO_CFG_BUSY BIT(31) #define MTK_PPE_FLOW_CFG 0x204 +#define MTK_PPE_MD_TOAP_BYP_CRSN0 BIT(1) +#define MTK_PPE_MD_TOAP_BYP_CRSN1 BIT(2) +#define MTK_PPE_MD_TOAP_BYP_CRSN2 BIT(3) #define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6) #define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7) #define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8) @@ -35,6 +38,8 @@ #define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18) #define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19) #define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20) +#define MTK_PPE_FLOW_CFG_IPV4_MAPE_EN BIT(21) +#define MTK_PPE_FLOW_CFG_IPV4_MAPT_EN BIT(22) #define MTK_PPE_IP_PROTO_CHK 0x208 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0) @@ -54,6 +59,7 @@ #define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14) #define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16) #define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18) +#define MTK_PPE_TB_CFG_INFO_SEL BIT(20) enum { MTK_PPE_SCAN_MODE_DISABLED, @@ -112,6 +118,9 @@ enum { #define MTK_PPE_DEFAULT_CPU_PORT 0x248 #define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4)) +#define MTK_PPE_DEFAULT_CPU_PORT1 0x24C +#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4)) + #define MTK_PPE_MTU_DROP 0x308 #define MTK_PPE_VLAN_MTU0 0x30c @@ -141,4 +150,5 @@ enum { #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) +#define MTK_PPE_SBW_CTRL 0x374 #endif -- 2.18.0