From ce13d745854f0fc0949b7e07038467881605867d Mon Sep 17 00:00:00 2001 From: Sujuan Chen Date: Tue, 18 Jan 2022 16:28:14 +0800 Subject: [PATCH] mt7986:add wed support for mt7986 Signed-off-by: Sujuan Chen --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 13 +- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 +- drivers/net/ethernet/mediatek/mtk_wed.c | 246 +++++++++++------- drivers/net/ethernet/mediatek/mtk_wed.h | 19 +- .../net/ethernet/mediatek/mtk_wed_debugfs.c | 42 +++ drivers/net/ethernet/mediatek/mtk_wed_regs.h | 114 ++++++-- 6 files changed, 301 insertions(+), 137 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 537416e..e12f523 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -3392,6 +3392,7 @@ static int mtk_probe(struct platform_device *pdev) { struct device_node *mac_np; struct mtk_eth *eth; + struct resource *res; int err, i; eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); @@ -3406,7 +3407,6 @@ static int mtk_probe(struct platform_device *pdev) return PTR_ERR(eth->base); if(eth->soc->has_sram) { - struct resource *res; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (unlikely(!res)) return -EINVAL; @@ -3484,17 +3484,16 @@ static int mtk_probe(struct platform_device *pdev) }; struct regmap *mirror; void __iomem *wdma; + u32 wdma_phy; if (!np || i >= ARRAY_SIZE(wdma_regs)) break; - mirror = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "mediatek,pcie-mirror"); - if (IS_ERR(mirror)) - break; - wdma = eth->base + wdma_regs[i]; - mtk_wed_add_hw(np, wdma, mirror, i); + if (res) + wdma_phy = res->start + wdma_regs[i]; + + mtk_wed_add_hw(np, wdma, wdma_phy, mirror, i); } for (i = 0; i < MTK_MAX_IRQ_NUM; i++) { diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 14e2abf..22a0e14 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -487,8 +487,8 @@ #define RX_DMA_SPORT_MASK 0x7 #endif -#define MTK_WDMA0_BASE 0x2800 -#define MTK_WDMA1_BASE 0x2c00 +#define MTK_WDMA0_BASE 0x4800 +#define MTK_WDMA1_BASE 0x4c00 /* QDMA descriptor txd4 */ #define TX_DMA_CHKSUM (0x7 << 29) diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c index f34c537..683a006 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c @@ -16,15 +16,6 @@ #include "mtk_wed.h" #include "mtk_ppe.h" -#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) - -#define MTK_WED_PKT_SIZE 1900 -#define MTK_WED_BUF_SIZE 2048 -#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) - -#define MTK_WED_TX_RING_SIZE 2048 -#define MTK_WED_WDMA_RING_SIZE 1024 - static struct mtk_wed_hw *hw_list[2]; static DEFINE_MUTEX(hw_lock); @@ -104,19 +95,20 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) struct mtk_wdma_desc *desc; dma_addr_t desc_phys; void **page_list; - int token = dev->wlan.token_start; int ring_size; int n_pages; int i, page_idx; - ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); + ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT + + MTK_WED_WDMA_RING_SIZE * 2; + n_pages = ring_size / MTK_WED_BUF_PER_PAGE; page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL); if (!page_list) return -ENOMEM; - dev->buf_ring.size = ring_size; + dev->buf_ring.size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); dev->buf_ring.pages = page_list; desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc), @@ -152,17 +144,16 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) buf_phys = page_phys; for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) { - u32 txd_size; - txd_size = dev->wlan.init_buf(buf, buf_phys, token++); + dev->wlan.init_buf(buf, buf_phys, 0); desc->buf0 = buf_phys; - desc->buf1 = buf_phys + txd_size; + desc->buf1 = buf_phys + MTK_WED_FBUF_SIZE; desc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, - txd_size) | + MTK_WED_FBUF_SIZE) | FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1, - MTK_WED_BUF_SIZE - txd_size) | - MTK_WDMA_DESC_CTRL_LAST_SEG1; + MTK_WED_BUF_SIZE - MTK_WED_FBUF_SIZE) | + MTK_WDMA_DESC_CTRL_LAST_SEG0; desc->info = 0; desc++; @@ -239,11 +230,34 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en) } static void -mtk_wed_stop(struct mtk_wed_device *dev) +mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en) { - int pcie_idx = !!pci_domain_nr(dev->wlan.pci_dev->bus); - regmap_write(dev->hw->mirror, pcie_idx * 4, 0); + u32 value; + if (en) { + + value |= BIT(9); + wed_w32(dev, MTK_WED_TXDP_CTRL, value); + + value &= (0x0000ffff); + value |= (0x0103 << 16); + wed_w32(dev, MTK_WED_TXP_DW1, value); + } else { + + value &= (0x0000ffff); + value |= (0x0100 << 16); + wed_w32(dev, MTK_WED_TXP_DW1, value); + + value &= ~(1 << 9); + wed_w32(dev, MTK_WED_TXDP_CTRL, value); + } + +} + + +static void +mtk_wed_stop(struct mtk_wed_device *dev) +{ mtk_wed_set_ext_int(dev, false); wed_clr(dev, MTK_WED_CTRL, @@ -291,32 +305,51 @@ mtk_wed_detach(struct mtk_wed_device *dev) mutex_unlock(&hw_lock); } +static void +mtk_wed_bus_init(struct mtk_wed_device *dev) +{ + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, + MTK_WED_WPDMA_INT_CTRL_SIG_SRC | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, dev->hw->index)); + + return; +} + static void mtk_wed_hw_init_early(struct mtk_wed_device *dev) { - int pcie_idx = !!pci_domain_nr(dev->wlan.pci_dev->bus); u32 mask, set; - u32 offset; mtk_wed_stop(dev); mtk_wed_reset(dev, MTK_WED_RESET_WED); + mtk_wed_bus_init(dev); + wed_w32(dev, MTK_WED_WPDMA_CFG_INT_STATUS, dev->wlan.wpdma_phys); + wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_phys + 0x4); + wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx); + wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree); + mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE | MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE | MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE; set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) | MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP | MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY; + wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set); - wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES); + wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy); + + wed_w32(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT); + - offset = dev->hw->index ? 0x04000400 : 0; - wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); - wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); + wed_w32(dev, MTK_WED_WDMA_OFFSET0, + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS, MTK_WDMA_INT_STATUS) | + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG, MTK_WDMA_GLO_CFG)); - wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(pcie_idx)); - wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); + wed_w32(dev, MTK_WED_WDMA_OFFSET1, + FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL,MTK_WDMA_RING_TX(0)) | + FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL, MTK_WDMA_RING_RX(0))); } static void @@ -326,35 +359,67 @@ mtk_wed_hw_init(struct mtk_wed_device *dev) return; dev->init_done = true; + mtk_wed_set_ext_int(dev, false); + wed_w32(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE | FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, - dev->buf_ring.size / 128) | + (dev->buf_ring.size + MTK_WED_WDMA_RING_SIZE * 2) / 128) | FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, - MTK_WED_TX_RING_SIZE / 256)); + (dev->buf_ring.size + MTK_WED_WDMA_RING_SIZE * 2) / 128)); wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys); - wed_w32(dev, MTK_WED_TX_BM_TKID, - FIELD_PREP(MTK_WED_TX_BM_TKID_START, - dev->wlan.token_start) | - FIELD_PREP(MTK_WED_TX_BM_TKID_END, - dev->wlan.token_start + dev->wlan.nbuf)); - wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE); wed_w32(dev, MTK_WED_TX_BM_DYN_THR, - FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) | + FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 0) | MTK_WED_TX_BM_DYN_THR_HI); + /* token setting */ + wed_w32(dev, MTK_WED_TX_TKID_CTRL, + MTK_WED_TX_TKID_CTRL_PAUSE | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM, + dev->buf_ring.size / 128) | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM, + dev->buf_ring.size / 128)); + + wed_w32(dev, MTK_WED_TX_TKID_TKID, + FIELD_PREP(MTK_WED_TX_TKID_START, + dev->wlan.token_start) | + FIELD_PREP(MTK_WED_TX_BM_TKID_END, + dev->wlan.token_start + dev->wlan.nbuf - 1)); + + wed_w32(dev, MTK_WED_TX_TKID_DYN_THR, + FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) | + MTK_WED_TX_TKID_DYN_THR_HI); mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); - wed_set(dev, MTK_WED_CTRL, - MTK_WED_CTRL_WED_TX_BM_EN | - MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); - wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE); + + wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE); + + /* wed_dma_ctrl */ + wed_set(dev, MTK_WED_WPDMA_CTRL, + MTK_WED_WPDMA_CTRL_SDL1_FIXED); + + wed_set(dev, MTK_WED_GLO_CFG, + MTK_WED_GLO_CFG_TX_DMA_EN | + MTK_WED_GLO_CFG_RX_DMA_EN); + + wed_set(dev, MTK_WED_WDMA_GLO_CFG, + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); + + wed_set(dev, MTK_WED_WPDMA_GLO_CFG, + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); + + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, + MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP | + MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV); } static void @@ -482,7 +547,7 @@ mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int size) { ring->desc = dma_alloc_coherent(dev->hw->dev, - size * sizeof(*ring->desc), + size * sizeof(*ring->desc) * 2, &ring->desc_phys, GFP_KERNEL); if (!ring->desc) return -ENOMEM; @@ -496,36 +561,35 @@ mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, static int mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size) { - struct mtk_wed_ring *wdma = &dev->tx_wdma[idx]; + if (dev->wdma_init) + return 0; - if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE)) - return -ENOMEM; + for (idx = 0; idx < MTK_WED_TX_QUEUES; idx++) { + struct mtk_wed_ring *wdma = &dev->tx_wdma[idx]; - wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, - wdma->desc_phys); - wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, - size); - wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); + if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE)) + return -ENOMEM; - wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, - wdma->desc_phys); - wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, - size); + wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, + wdma->desc_phys); + wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, + size); + wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); + wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, + wdma->desc_phys); + wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, + size); + } + + dev->wdma_init = true; return 0; } static void mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) { - int pcie_idx = !!pci_domain_nr(dev->wlan.pci_dev->bus); u32 wdma_mask; - u32 val; - int i; - - for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) - if (!dev->tx_wdma[i].desc) - mtk_wed_wdma_ring_setup(dev, i, 16); wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); @@ -537,17 +601,24 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) MTK_WED_CTRL_WED_TX_BM_EN | MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); - wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS); + /* initail tx interrupt trigger */ + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX, + MTK_WED_WPDMA_INT_CTRL_TX_DONE_EN0 | + MTK_WED_WPDMA_INT_CTRL_TX_DONE_CLR0 | + MTK_WED_WPDMA_INT_CTRL_TX_DONE_EN1 | + MTK_WED_WPDMA_INT_CTRL_TX_DONE_CLR1 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_DONE_TRIG0, 30) | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_DONE_TRIG1, 31)); - wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, - MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | - MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); - - wed_set(dev, MTK_WED_WPDMA_INT_CTRL, - MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE, + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN0 | + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR0 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG0, 2)); wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); - wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); + wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask); + + wed_set(dev, MTK_WED_WDMA_INT_CTRL, dev->wdma_idx); wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); @@ -555,24 +626,9 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); wed_w32(dev, MTK_WED_INT_MASK, irq_mask); - wed_set(dev, MTK_WED_GLO_CFG, - MTK_WED_GLO_CFG_TX_DMA_EN | - MTK_WED_GLO_CFG_RX_DMA_EN); - wed_set(dev, MTK_WED_WPDMA_GLO_CFG, - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); - wed_set(dev, MTK_WED_WDMA_GLO_CFG, - MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); - mtk_wed_set_ext_int(dev, true); - val = dev->wlan.wpdma_phys | - MTK_PCIE_MIRROR_MAP_EN | - FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); - if (dev->hw->index) - val |= BIT(1); - val |= BIT(0); - regmap_write(dev->hw->mirror, pcie_idx * 4, val); + mtk_wed_set_512_support(dev, true); dev->running = true; } @@ -583,9 +639,6 @@ mtk_wed_attach(struct mtk_wed_device *dev) struct mtk_wed_hw *hw; int ret = 0; - if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1) - return -ENODEV; - if (!try_module_get(THIS_MODULE)) return -ENODEV; @@ -669,14 +722,14 @@ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs) * and WLAN. The WLAN driver accesses the ring index registers through * WED */ - ring->reg_base = MTK_WED_RING_RX(1); + ring->reg_base = MTK_WED_RING_RX(0); ring->wpdma = regs; for (i = 0; i < 12; i += 4) { u32 val = readl(regs + i); - wed_w32(dev, MTK_WED_RING_RX(1) + i, val); - wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val); + wed_w32(dev, MTK_WED_RING_RX(0) + i, val); + wed_w32(dev, MTK_WED_WPDMA_RING_RX(0) + i, val); } return 0; @@ -711,7 +764,7 @@ mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask) } void mtk_wed_add_hw(struct device_node *np, void __iomem *wdma, - void __iomem *mirror, int index) + u32 wdma_phy, void __iomem *mirror, int index) { static const struct mtk_wed_ops wed_ops = { .attach = mtk_wed_attach, @@ -759,13 +812,10 @@ void mtk_wed_add_hw(struct device_node *np, void __iomem *wdma, hw->regs = regs; hw->dev = &pdev->dev; hw->wdma = wdma; + hw->wdma_phy = wdma_phy; hw->index = index; hw->irq = irq; - hw->mirror = mirror; - if (!index) { - regmap_write(mirror, 0, 0); - regmap_write(mirror, 4, 0); - } + mtk_wed_hw_add_debugfs(hw); hw_list[index] = hw; diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h index 513464e..7166450 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed.h +++ b/drivers/net/ethernet/mediatek/mtk_wed.h @@ -7,6 +7,19 @@ #include #include #include +#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) + +#define MTK_WED_PKT_SIZE 1900 +#define MTK_WED_BUF_SIZE 2048 +#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) + +#define MTK_WED_TX_RING_SIZE 2048 +#define MTK_WED_WDMA_RING_SIZE 512//1024 +#define MTK_WED_MAX_GROUP_SIZE 0x100 +#define MTK_WED_VLD_GROUP_SIZE 0x40 +#define MTK_WED_PER_GROUP_PKT 128 + +#define MTK_WED_FBUF_SIZE 128 struct mtk_wed_hw { struct device_node *node; @@ -18,6 +31,8 @@ struct mtk_wed_hw { struct mtk_wed_device *wed_dev; u32 debugfs_reg; u32 num_flows; + u32 wdma_phy; + u32 token_id; char dirname[5]; int irq; int index; @@ -88,12 +103,12 @@ wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val) } #ifdef CONFIG_NET_MEDIATEK_SOC_WED -void mtk_wed_add_hw(struct device_node *np, void __iomem *wdma, +void mtk_wed_add_hw(struct device_node *np, void __iomem *wdma, u32 wdma_phy, void __iomem *mirror, int index); void mtk_wed_exit(void); #else static inline void -mtk_wed_add_hw(struct device_node *np, void __iomem *wdma, +mtk_wed_add_hw(struct device_node *np, void __iomem *wdma, u32 wdma_phy, void __iomem *mirror, int index) { } diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c index a81d3fd..8d995b7 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c +++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c @@ -159,6 +159,46 @@ mtk_wed_reg_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mtk_wed_reg_get, mtk_wed_reg_set, "0x%08llx\n"); +static int +wed_token_txd_show(struct seq_file *s, void *data) +{ + struct mtk_wed_hw *hw = s->private; + struct mtk_wed_device *dev = hw->wed_dev; + void **page_list = dev->buf_ring.pages; + int token = dev->wlan.token_start; + u32 val = hw->token_id, size = 1; + int page_idx = (val - token) / 2; + int i; + + if (val < token) { + size = val; + page_idx = 0; + } + + for (i = 0; i < size; i += MTK_WED_BUF_PER_PAGE) { + void *page = page_list[page_idx++]; + void *buf; + int j; + + if (!page) + break; + + buf = page_to_virt(page); + + for (j = 0; j < MTK_WED_BUF_PER_PAGE; j++) { + printk("[TXD]:token id = %d\n", token + 2 * (page_idx - 1) + j); + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)buf, 80, false); + seq_printf(s, "\n"); + + buf += MTK_WED_BUF_SIZE; + } + } + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(wed_token_txd); + void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw) { struct dentry *dir; @@ -172,4 +212,6 @@ void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw) debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg); debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval); debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops); + debugfs_create_u32("token_id", 0600, dir, &hw->token_id); + debugfs_create_file_unsafe("token_txd", 0600, dir, hw, &wed_token_txd_fops); } diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h index cbeaa08..b7dc424 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h @@ -4,9 +4,9 @@ #ifndef __MTK_WED_REGS_H #define __MTK_WED_REGS_H -#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0) -#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) -#define MTK_WDMA_DESC_CTRL_BURST BIT(16) +#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(13, 0) +#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(14) +#define MTK_WDMA_DESC_CTRL_BURST BIT(15) #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16) #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30) #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31) @@ -41,6 +41,7 @@ struct mtk_wdma_desc { #define MTK_WED_CTRL_RESERVE_EN BIT(12) #define MTK_WED_CTRL_RESERVE_BUSY BIT(13) #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24) +#define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25) #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28) #define MTK_WED_EXT_INT_STATUS 0x020 @@ -49,29 +50,40 @@ struct mtk_wdma_desc { #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4) #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8) #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9) -#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12) -#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13) +#define MTK_WED_EXT_INT_STATUS_TX_TKID_LO_TH BIT(10) +#define MTK_WED_EXT_INT_STATUS_TX_TKID_HI_TH BIT(11) +#define MTK_WED_EXT_INT_STATUS_RX_FREE_AT_EMPTY BIT(12) +#define MTK_WED_EXT_INT_STATUS_RX_FBUF_DMAD_ER BIT(13) #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16) #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17) #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18) #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19) #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20) #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21) -#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR BIT(22) +#define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22) +#define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23) #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24) +#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25) +#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26) +#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27) + + #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \ MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \ MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \ + MTK_WED_EXT_INT_STATUS_RX_FREE_AT_EMPTY | \ + MTK_WED_EXT_INT_STATUS_RX_FBUF_DMAD_ER | \ MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \ MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \ + MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT | \ MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \ - MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \ - MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR) + MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR | \ + MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR) #define MTK_WED_EXT_INT_MASK 0x028 +#define MTK_WED_EXT_INT_MASK1 0x02c +#define MTK_WED_EXT_INT_MASK2 0x030 -#define MTK_WED_STATUS 0x060 -#define MTK_WED_STATUS_TX GENMASK(15, 8) #define MTK_WED_TX_BM_CTRL 0x080 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0) @@ -80,10 +92,6 @@ struct mtk_wdma_desc { #define MTK_WED_TX_BM_BASE 0x084 -#define MTK_WED_TX_BM_TKID 0x088 -#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) -#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) - #define MTK_WED_TX_BM_BUF_LEN 0x08c #define MTK_WED_TX_BM_INTF 0x09c @@ -96,6 +104,23 @@ struct mtk_wdma_desc { #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0) #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16) +#define MTK_WED_TX_TKID_CTRL 0x0c0 +#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0) +#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16) +#define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28) + +#define MTK_WED_TX_TKID_TKID 0x0c8 +#define MTK_WED_TX_TKID_START GENMASK(15, 0) +#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) + +#define MTK_WED_TX_TKID_DYN_THR 0x0e0 +#define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0) +#define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16) + +#define MTK_WED_TXP_DW0 0x120 +#define MTK_WED_TXP_DW1 0x124 +#define MTK_WED_TXDP_CTRL 0x130 + #define MTK_WED_INT_STATUS 0x200 #define MTK_WED_INT_MASK 0x204 @@ -139,37 +164,60 @@ struct mtk_wdma_desc { #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1) #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2) #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3) -#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) -#define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6) -#define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) -#define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8) -#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9) -#define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10) -#define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) -#define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13) -#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22) -#define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24) -#define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) -#define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27) -#define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4) +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5) +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6) +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7) +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16) +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19) +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20) +#define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21) +#define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24) +#define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28) #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29) +#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30) #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) #define MTK_WED_WPDMA_RESET_IDX 0x50c #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0) #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16) +#define MTK_WED_WPDMA_CTRL 0x518 +#define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31) + #define MTK_WED_WPDMA_INT_CTRL 0x520 #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21) +#define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22) +#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16) + #define MTK_WED_WPDMA_INT_MASK 0x524 +#define MTK_WED_WPDMA_INT_CTRL_TX 0x530 +#define MTK_WED_WPDMA_INT_CTRL_TX_DONE_EN0 BIT(0) +#define MTK_WED_WPDMA_INT_CTRL_TX_DONE_CLR0 BIT(1) +#define MTK_WED_WPDMA_INT_CTRL_TX_DONE_TRIG0 GENMASK(6, 2) +#define MTK_WED_WPDMA_INT_CTRL_TX_DONE_EN1 BIT(8) +#define MTK_WED_WPDMA_INT_CTRL_TX_DONE_CLR1 BIT(9) +#define MTK_WED_WPDMA_INT_CTRL_TX_DONE_TRIG1 GENMASK(14, 10) + +#define MTK_WED_WPDMA_INT_CTRL_RX 0x534 + +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538 +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN0 BIT(0) +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR0 BIT(1) +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG0 GENMASK(6, 2) + #define MTK_WED_PCIE_CFG_BASE 0x560 #define MTK_WED_PCIE_INT_TRIGGER 0x570 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16) -#define MTK_WED_WPDMA_CFG_BASE 0x580 +#define MTK_WED_WPDMA_CFG_INT_STATUS 0x580 +#define MTK_WED_WPDMA_CFG_INT_MASK 0x584 +#define MTK_WED_WPDMA_CFG_TX 0x588 +#define MTK_WED_WPDMA_CFG_TX_FREE 0x58c + #define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4) #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4) @@ -203,14 +251,22 @@ struct mtk_wdma_desc { #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16) #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24) +#define MTK_WED_WDMA_INT_CLR 0xa24 +#define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16) + #define MTK_WED_WDMA_INT_TRIGGER 0xa28 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16) #define MTK_WED_WDMA_INT_CTRL 0xa2c #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16) +#define MTK_WED_WDMA_CFG_BASE 0xaa0 #define MTK_WED_WDMA_OFFSET0 0xaa4 #define MTK_WED_WDMA_OFFSET1 0xaa8 +#define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0) +#define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16) +#define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0) +#define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16) #define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4) #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4) @@ -221,6 +277,7 @@ struct mtk_wdma_desc { #define MTK_WED_RING_OFS_CPU_IDX 0x08 #define MTK_WED_RING_OFS_DMA_IDX 0x0c +#define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10) #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10) #define MTK_WDMA_GLO_CFG 0x204 @@ -229,6 +286,7 @@ struct mtk_wdma_desc { #define MTK_WDMA_RESET_IDX 0x208 #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0) #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16) +#define MTK_WDMA_INT_STATUS 0x220 #define MTK_WDMA_INT_MASK 0x228 #define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0) -- 2.18.0