From 7911774f14f28739b6902a92b3f8727b7a1c2024 Mon Sep 17 00:00:00 2001 From: Shayne Chen Date: Wed, 7 Sep 2022 12:15:22 +0800 Subject: [PATCH] wifi: mt76: mt7996: add internal debug tool Change-Id: I04f9ab7cb762d1ba7e7217908fe9beae20fba282 --- mt76_connac_mcu.h | 1 + mt7996/Makefile | 2 +- mt7996/debugfs.c | 19 +- mt7996/mac.c | 31 + mt7996/mcu.c | 4 + mt7996/mcu.h | 8 + mt7996/mt7996.h | 26 + mt7996/mtk_debug_i.h | 1623 ++++++++++++++++++++++++++++++++++++++ mt7996/mtk_debugfs.c | 15 + mt7996/mtk_debugfs_i.c | 1669 ++++++++++++++++++++++++++++++++++++++++ mt7996/mtk_mcu_i.c | 17 + mt7996/mtk_mcu_i.h | 16 + 12 files changed, 3429 insertions(+), 2 deletions(-) create mode 100644 mt7996/mtk_debug_i.h create mode 100644 mt7996/mtk_debugfs_i.c create mode 100644 mt7996/mtk_mcu_i.c create mode 100644 mt7996/mtk_mcu_i.h diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h index d74fd2dd..aeac7ba9 100644 --- a/mt76_connac_mcu.h +++ b/mt76_connac_mcu.h @@ -1243,6 +1243,7 @@ enum { MCU_UNI_CMD_CHANNEL_SWITCH = 0x34, MCU_UNI_CMD_THERMAL = 0x35, MCU_UNI_CMD_VOW = 0x37, + MCU_UNI_CMD_MEC = 0x3A, MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40, MCU_UNI_CMD_TESTMODE_CTRL = 0x46, MCU_UNI_CMD_PRECAL_RESULT = 0x47, diff --git a/mt7996/Makefile b/mt7996/Makefile index 8dbbc34c..08435bda 100644 --- a/mt7996/Makefile +++ b/mt7996/Makefile @@ -12,4 +12,4 @@ mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o mt7996e-$(CONFIG_NL80211_TESTMODE) += testmode.o -mt7996e-y += mtk_debugfs.o mtk_mcu.o +mt7996e-y += mtk_debugfs.o mtk_mcu.o mtk_debugfs_i.o mtk_mcu_i.o diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c index 49c815a5..bacb9a76 100644 --- a/mt7996/debugfs.c +++ b/mt7996/debugfs.c @@ -436,6 +436,14 @@ mt7996_fw_debug_bin_set(void *data, u64 val) relay_reset(dev->relay_fwlog); +#ifdef CONFIG_MTK_DEBUG + dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false; + dev->dbg.dump_txd = val & BIT(5) ? true : false; + dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false; + dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false; + dev->dbg.dump_rx_raw = val & BIT(8) ? true : false; +#endif + if (dev->relay_fwlog && !val) { relay_close(dev->relay_fwlog); dev->relay_fwlog = NULL; @@ -846,8 +854,12 @@ int mt7996_init_debugfs(struct mt7996_phy *phy) mt7996_rdd_monitor); } - if (phy == &dev->phy) + if (phy == &dev->phy) { dev->debugfs_dir = dir; +#ifdef CONFIG_MTK_DEBUG + mt7996_mtk_init_debugfs_internal(phy, dir); +#endif + } #ifdef CONFIG_MTK_DEBUG debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx); @@ -912,7 +924,12 @@ void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len) { +#ifdef CONFIG_MTK_DEBUG + if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC && + get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC) +#else if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) +#endif return false; if (dev->relay_fwlog) diff --git a/mt7996/mac.c b/mt7996/mac.c index 4706cb66..ab48ec69 100644 --- a/mt7996/mac.c +++ b/mt7996/mac.c @@ -672,6 +672,11 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q, u8 hw_aggr = false; struct mt7996_sta *msta = NULL; +#ifdef CONFIG_MTK_DEBUG + if (dev->dbg.dump_rx_raw) + mt7996_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0); + mt7996_dump_bmac_rxd_info(dev, rxd); +#endif hw_aggr = status->aggr; memset(status, 0, sizeof(*status)); @@ -845,6 +850,10 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, enum mt76_rxq_id q, } hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; +#ifdef CONFIG_MTK_DEBUG + if (dev->dbg.dump_rx_pkt) + mt7996_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap); +#endif if (hdr_trans && ieee80211_has_morefrags(fc)) { if (mt7996_reverse_frag0_hdr_trans(skb, hdr_gap)) return -EINVAL; @@ -1125,6 +1134,9 @@ static int mt7996_tx_prepare_skb_pao(struct mt76_dev *mdev, void *txwi_ptr, struct mt76_wcid *wcid, struct mt76_tx_info *tx_info) { +#ifdef CONFIG_MTK_DEBUG + struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); +#endif struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); struct ieee80211_vif *vif = info->control.vif; struct mt7996_vif *mvif; @@ -1223,6 +1235,17 @@ mt7996_tx_prepare_skb_pao(struct mt76_dev *mdev, void *txwi_ptr, tx_info->buf[1].skip_unmap = true; tx_info->nbuf = 1; +#ifdef CONFIG_MTK_DEBUG + dev->dbg.pao_nbuf[nbuf-1]++; + + mt7996_dump_bmac_txd_info(dev, (__le32 *)txwi, true, false); + + if (dev->dbg.dump_txd) + mt7996_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0); + if (dev->dbg.dump_tx_pkt) + mt7996_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0); +#endif + return 0; } @@ -1325,6 +1348,14 @@ int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, tx_info->buf[1].skip_unmap = true; tx_info->nbuf = MT_CT_DMA_BUF_NUM; +#ifdef CONFIG_MTK_DEBUG + if (dev->dbg.dump_txd) + mt7996_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0); + if (dev->dbg.dump_tx_pkt) + mt7996_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0); + mt7996_dump_bmac_txd_info(dev, (__le32 *)txwi, true, false); +#endif + return 0; } diff --git a/mt7996/mcu.c b/mt7996/mcu.c index 415a62dc..3c77fd10 100644 --- a/mt7996/mcu.c +++ b/mt7996/mcu.c @@ -301,6 +301,10 @@ mt7996_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, mcu_txd->s2d_index = MCU_S2D_H2N; exit: +#ifdef CONFIG_MTK_DEBUG + if (dev->dbg.dump_mcu_pkt) + mt7996_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0); +#endif if (wait_seq) *wait_seq = seq; diff --git a/mt7996/mcu.h b/mt7996/mcu.h index 10e3799f..5e75585f 100644 --- a/mt7996/mcu.h +++ b/mt7996/mcu.h @@ -754,6 +754,14 @@ enum { UNI_RRO_SET_FLUSH_TIMEOUT }; +enum { + UNI_MEC_READ_INFO = 0, + UNI_MEC_AMSDU_ALGO_EN_STA, + UNI_MEC_AMSDU_PARA_STA, + UNI_MEC_AMSDU_ALGO_THRESHOLD, + UNI_MEC_IFAC_SPEED, +}; + enum{ UNI_CMD_SR_ENABLE = 0x1, UNI_CMD_SR_ENABLE_SD, diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h index fcf8d046..f9942f64 100644 --- a/mt7996/mt7996.h +++ b/mt7996/mt7996.h @@ -553,6 +553,18 @@ struct mt7996_dev { u32 fw_dbg_module; u8 fw_dbg_lv; u32 bcn_total_cnt[__MT_MAX_BAND]; + + bool dump_mcu_pkt:1; + bool dump_txd:1; + bool dump_tx_pkt:1; + bool dump_rx_pkt:1; + bool dump_rx_raw:1; + u8 dump_ple_txd; + u32 token_idx; + u32 rxd_read_cnt; + u32 txd_read_cnt; + u32 fid_idx; + u32 pao_nbuf[MT7996_TX_PAO_NUM_MAX]; } dbg; #endif }; @@ -889,6 +901,20 @@ int mt7996_vendor_amnt_sta_remove(struct mt7996_phy *phy, #ifdef CONFIG_MTK_DEBUG int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir); + +#define PKT_BIN_DEBUG_MAGIC 0xc8763123 +enum { + PKT_BIN_DEBUG_MCU, + PKT_BIN_DEBUG_TXD, + PKT_BIN_DEBUG_TX, + PKT_BIN_DEBUG_RX, + PKT_BIN_DEBUG_RX_RAW, +}; + +void mt7996_packet_log_to_host(struct mt7996_dev *dev, const void *data, int len, int type, int des_len); +void mt7996_dump_bmac_rxd_info(struct mt7996_dev *dev, __le32 *rxd); +void mt7996_dump_bmac_txd_info(struct mt7996_dev *dev, __le32 *txd, bool is_hif_txd, bool dump_txp); +int mt7996_mtk_init_debugfs_internal(struct mt7996_phy *phy, struct dentry *dir); #endif #endif diff --git a/mt7996/mtk_debug_i.h b/mt7996/mtk_debug_i.h new file mode 100644 index 00000000..aabd4781 --- /dev/null +++ b/mt7996/mtk_debug_i.h @@ -0,0 +1,1623 @@ +#ifndef __MTK_DEBUG_I_H +#define __MTK_DEBUG_I_H + +#ifdef CONFIG_MTK_DEBUG + +struct bin_debug_hdr { + __le32 magic_num; + __le16 serial_id; + __le16 msg_type; + __le16 len; + __le16 des_len; /* descriptor len for rxd */ +} __packed; + +enum umac_port { + ENUM_UMAC_HIF_PORT_0 = 0, + ENUM_UMAC_CPU_PORT_1 = 1, + ENUM_UMAC_LMAC_PORT_2 = 2, + ENUM_PLE_CTRL_PSE_PORT_3 = 3, + ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4 +}; + +/* N9 MCU QUEUE LIST */ +enum umac_cpu_port_queue_idx { + ENUM_UMAC_CTX_Q_0 = 0, + ENUM_UMAC_CTX_Q_1 = 1, + ENUM_UMAC_CTX_Q_2 = 2, + ENUM_UMAC_CTX_Q_3 = 3, + ENUM_UMAC_CRX = 0, + ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4 +}; + +/* LMAC PLE For PSE Control P3 */ +enum umac_ple_ctrl_port3_queue_idx { + ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e, + ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f, + ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2 +}; + +/* PSE PLE QUEUE */ +#define CR_NUM_OF_AC 9 +#define ALL_CR_NUM_OF_ALL_AC (CR_NUM_OF_AC * 4) +struct bmac_queue_info { + char *QueueName; + u32 Portid; + u32 Queueid; + u32 tgid; +}; + +struct bmac_queue_info_t { + char *QueueName; + u32 Portid; + u32 Queueid; +}; + +/* PLE AMSDU */ +#define WF_PLE_TOP_BASE 0x820c0000 + +#define WF_PLE_TOP_AMSDU_PACK_1_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e0) // 10E0 +#define WF_PLE_TOP_AMSDU_PACK_2_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e4) // 10E4 +#define WF_PLE_TOP_AMSDU_PACK_3_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e8) // 10E8 +#define WF_PLE_TOP_AMSDU_PACK_4_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10ec) // 10EC +#define WF_PLE_TOP_AMSDU_PACK_5_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f0) // 10F0 +#define WF_PLE_TOP_AMSDU_PACK_6_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f4) // 10F4 +#define WF_PLE_TOP_AMSDU_PACK_7_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f8) // 10F8 +#define WF_PLE_TOP_AMSDU_PACK_8_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10fc) // 10FC + +/* PLE */ +#define WF_PLE_TOP_PBUF_CTRL_ADDR (WF_PLE_TOP_BASE + 0x04) // 0004 + +#define WF_PLE_TOP_PG_HIF_GROUP_ADDR (WF_PLE_TOP_BASE + 0x0c) // 000C +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x10) // 0010 +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x14) // 0014 +#define WF_PLE_TOP_PG_CPU_GROUP_ADDR (WF_PLE_TOP_BASE + 0x18) // 0018 +#define WF_PLE_TOP_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x360) // 0360 + +#define WF_PLE_TOP_DIS_STA_MAP0_ADDR (WF_PLE_TOP_BASE + 0x100) // 0100 +#define WF_PLE_TOP_DIS_STA_MAP1_ADDR (WF_PLE_TOP_BASE + 0x104) // 0104 +#define WF_PLE_TOP_DIS_STA_MAP2_ADDR (WF_PLE_TOP_BASE + 0x108) // 0108 +#define WF_PLE_TOP_DIS_STA_MAP3_ADDR (WF_PLE_TOP_BASE + 0x10c) // 010C +#define WF_PLE_TOP_DIS_STA_MAP4_ADDR (WF_PLE_TOP_BASE + 0x110) // 0110 +#define WF_PLE_TOP_DIS_STA_MAP5_ADDR (WF_PLE_TOP_BASE + 0x114) // 0114 +#define WF_PLE_TOP_DIS_STA_MAP6_ADDR (WF_PLE_TOP_BASE + 0x118) // 0118 +#define WF_PLE_TOP_DIS_STA_MAP7_ADDR (WF_PLE_TOP_BASE + 0x11c) // 011C +#define WF_PLE_TOP_DIS_STA_MAP8_ADDR (WF_PLE_TOP_BASE + 0x120) // 0120 + +#define WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x378) // 0378 +#define WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x37c) // 037C + +#define WF_PLE_TOP_FREEPG_CNT_ADDR (WF_PLE_TOP_BASE + 0x3a0) // 03A0 +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PLE_TOP_BASE + 0x3a4) // 03A4 +#define WF_PLE_TOP_HIF_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3a8) // 03A8 +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3ac) // 03AC +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b0) // 03B0 +#define WF_PLE_TOP_CPU_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b4) // 03B4 + +#define WF_PLE_TOP_FL_QUE_CTRL_0_ADDR (WF_PLE_TOP_BASE + 0x3e0) // 03E0 +#define WF_PLE_TOP_FL_QUE_CTRL_1_ADDR (WF_PLE_TOP_BASE + 0x3e4) // 03E4 +#define WF_PLE_TOP_FL_QUE_CTRL_2_ADDR (WF_PLE_TOP_BASE + 0x3e8) // 03E8 +#define WF_PLE_TOP_FL_QUE_CTRL_3_ADDR (WF_PLE_TOP_BASE + 0x3ec) // 03EC + +#define WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x600) // 0600 +#define WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x604) // 0604 +#define WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x608) // 0608 +#define WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x60c) // 060C +#define WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x610) // 0610 +#define WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x614) // 0614 +#define WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x618) // 0618 +#define WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x61c) // 061C +#define WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x620) // 0620 + +#define WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x700) // 0700 +#define WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x704) // 0704 +#define WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x708) // 0708 +#define WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x70c) // 070C +#define WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x710) // 0710 +#define WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x714) // 0714 +#define WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x718) // 0718 +#define WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x71c) // 071C +#define WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x720) // 0720 + +#define WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x800) // 0800 +#define WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x804) // 0804 +#define WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x808) // 0808 +#define WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x80c) // 080C +#define WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x810) // 0810 +#define WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x814) // 0814 +#define WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x818) // 0818 +#define WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x81c) // 081C +#define WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x820) // 0820 + +#define WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x900) // 0900 +#define WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x904) // 0904 +#define WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x908) // 0908 +#define WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x90c) // 090C +#define WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x910) // 0910 +#define WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x914) // 0914 +#define WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x918) // 0918 +#define WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x91c) // 091C +#define WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x920) // 0920 + +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_ADDR WF_PLE_TOP_QUEUE_EMPTY_ADDR +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK 0x01000000 // ALL_AC_EMPTY[24] +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_SHFT 24 + +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31] +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31 +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x07FE0000 // PBUF_OFFSET[26..17] +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17 +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00001FFF // TOTAL_PAGE_NUM[12..0] +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0 + +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x1FFF0000 // FFA_CNT[28..16] +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16 +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00001FFF // FREEPG_CNT[12..0] +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0 + +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x1FFF0000 // FREEPG_TAIL[28..16] +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16 +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00001FFF // FREEPG_HEAD[12..0] +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0 + +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK 0x1FFF0000 // HIF_MAX_QUOTA[28..16] +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT 16 +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK 0x00001FFF // HIF_MIN_QUOTA[12..0] +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT 0 + +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK 0x1FFF0000 // HIF_SRC_CNT[28..16] +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT 16 +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK 0x00001FFF // HIF_RSV_CNT[12..0] +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT 0 + +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_MASK 0x1FFF0000 // HIF_WMTXD_MAX_QUOTA[28..16] +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_SHFT 16 +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_MASK 0x00001FFF // HIF_WMTXD_MIN_QUOTA[12..0] +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_SHFT 0 + +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_MASK 0x1FFF0000 // HIF_WMTXD_SRC_CNT[28..16] +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_SHFT 16 +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_MASK 0x00001FFF // HIF_WMTXD_RSV_CNT[12..0] +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_SHFT 0 + +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK 0x1FFF0000 // HIF_TXCMD_MAX_QUOTA[28..16] +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT 16 +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK 0x00001FFF // HIF_TXCMD_MIN_QUOTA[12..0] +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT 0 + +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK 0x1FFF0000 // HIF_TXCMD_SRC_CNT[28..16] +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT 16 +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK 0x00001FFF // HIF_TXCMD_RSV_CNT[12..0] +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT 0 + +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x1FFF0000 // CPU_MAX_QUOTA[28..16] +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16 +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00001FFF // CPU_MIN_QUOTA[12..0] +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0 + +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x1FFF0000 // CPU_SRC_CNT[28..16] +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16 +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00001FFF // CPU_RSV_CNT[12..0] +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0 + +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31] +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31 +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24] +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24 +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_MASK 0x00FFF000 // FL_BUFFER_ADDR[23..12] +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_SHFT 12 +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK 0x00000FFF // Q_BUF_WLANID[11..0] +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0 + +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_MASK 0xC0000000 // Q_BUF_TGID[31..30] +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_SHFT 30 +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_MASK 0x30000000 // Q_BUF_PID[29..28] +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT 28 + +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x1FFF0000 // QUEUE_TAIL_FID[28..16] +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16 +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00001FFF // QUEUE_HEAD_FID[12..0] +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0 + +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PLE_TOP_FL_QUE_CTRL_3_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00001FFF // QUEUE_PKT_NUM[12..0] +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0 + +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_TGID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_TGID_MASK 0x00300000 // Q_BUF_TGID[21..20] +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_TGID_SHFT 20 +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_MASK 0x00030000 // Q_BUF_PID[17..16] +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 16 +/* PSE */ +#define WF_PSE_TOP_BASE 0x820c8000 + +#define WF_PSE_TOP_PBUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x04) // 8004 +#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) // 80B0 +#define WF_PSE_TOP_QUEUE_EMPTY_1_ADDR (WF_PSE_TOP_BASE + 0xBC) // 80BC +#define WF_PSE_TOP_PG_HIF0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x110) // 8110 +#define WF_PSE_TOP_PG_HIF1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x114) // 8114 +#define WF_PSE_TOP_PG_CPU_GROUP_ADDR (WF_PSE_TOP_BASE + 0x118) // 8118 +#define WF_PSE_TOP_PG_PLE_GROUP_ADDR (WF_PSE_TOP_BASE + 0x11C) // 811C +#define WF_PSE_TOP_PG_PLE1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x120) // 8120 +#define WF_PSE_TOP_PG_LMAC0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x124) // 8124 +#define WF_PSE_TOP_PG_LMAC1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x128) // 8128 +#define WF_PSE_TOP_PG_LMAC2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x12C) // 812C +#define WF_PSE_TOP_PG_LMAC3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x130) // 8130 +#define WF_PSE_TOP_PG_MDP_GROUP_ADDR (WF_PSE_TOP_BASE + 0x134) // 8134 +#define WF_PSE_TOP_PG_MDP2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x13C) // 813C +#define WF_PSE_TOP_PG_HIF2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x140) // 8140 +#define WF_PSE_TOP_PG_MDP3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x144) // 8144 +#define WF_PSE_TOP_HIF0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x150) // 8150 +#define WF_PSE_TOP_HIF1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x154) // 8154 +#define WF_PSE_TOP_CPU_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x158) // 8158 +#define WF_PSE_TOP_PLE_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x15C) // 815C +#define WF_PSE_TOP_PLE1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x160) // 8160 +#define WF_PSE_TOP_LMAC0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x164) // 8164 +#define WF_PSE_TOP_LMAC1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x168) // 8168 +#define WF_PSE_TOP_LMAC2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x16C) // 816C +#define WF_PSE_TOP_LMAC3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x170) // 8170 +#define WF_PSE_TOP_MDP_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x174) // 8174 +#define WF_PSE_TOP_MDP2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x17C) // 817C +#define WF_PSE_TOP_HIF2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x180) // 8180 +#define WF_PSE_TOP_MDP3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x184) // 8184 +#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) // 81B0 +#define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) // 81B4 +#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) // 81B8 +#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) // 81BC +#define WF_PSE_TOP_FREEPG_CNT_ADDR (WF_PSE_TOP_BASE + 0x380) // 8380 +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PSE_TOP_BASE + 0x384) // 8384 + +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31] +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31 +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17] +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17 +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0] +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0 + +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK 0x80000000 // RLS_Q_EMTPY[31] +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT 31 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_MASK 0x10000000 // CPU_Q4_EMPTY[28] +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_SHFT 28 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK 0x08000000 // MDP_RXIOC1_QUEUE_EMPTY[27] +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT 27 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK 0x04000000 // MDP_TXIOC1_QUEUE_EMPTY[26] +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT 26 +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK 0x02000000 // SEC_TX1_QUEUE_EMPTY[25] +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT 25 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK 0x01000000 // MDP_TX1_QUEUE_EMPTY[24] +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT 24 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK 0x00800000 // MDP_RXIOC_QUEUE_EMPTY[23] +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT 23 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK 0x00400000 // MDP_TXIOC_QUEUE_EMPTY[22] +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT 22 +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK 0x00200000 // SFD_PARK_QUEUE_EMPTY[21] +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT 21 +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK 0x00100000 // SEC_RX_QUEUE_EMPTY[20] +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT 20 +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK 0x00080000 // SEC_TX_QUEUE_EMPTY[19] +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT 19 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK 0x00040000 // MDP_RX_QUEUE_EMPTY[18] +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT 18 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK 0x00020000 // MDP_TX_QUEUE_EMPTY[17] +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT 17 +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK 0x00010000 // LMAC_TX_QUEUE_EMPTY[16] +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT 16 + +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK 0x00000008 // CPU_Q3_EMPTY[3] +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT 3 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK 0x00000004 // CPU_Q2_EMPTY[2] +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT 2 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK 0x00000002 // CPU_Q1_EMPTY[1] +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT 1 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK 0x00000001 // CPU_Q0_EMPTY[0] +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT 0 + +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_MASK 0x20000000 // HIF_13_EMPTY[29] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_SHFT 29 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_MASK 0x10000000 // HIF_12_EMPTY[28] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_SHFT 28 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_MASK 0x08000000 // HIF_11_EMPTY[27] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_SHFT 27 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_MASK 0x04000000 // HIF_10_EMPTY[26] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_SHFT 26 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_MASK 0x02000000 // HIF_9_EMPTY[25] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_SHFT 25 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_MASK 0x01000000 // HIF_8_EMPTY[24] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_SHFT 24 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_MASK 0x00800000 // HIF_7_EMPTY[23] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_SHFT 23 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_MASK 0x00400000 // HIF_6_EMPTY[22] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_SHFT 22 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_MASK 0x00200000 // HIF_5_EMPTY[21] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_SHFT 21 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_MASK 0x00100000 // HIF_4_EMPTY[20] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_SHFT 20 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_MASK 0x00080000 // HIF_3_EMPTY[19] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_SHFT 19 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_MASK 0x00040000 // HIF_2_EMPTY[18] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_SHFT 18 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_MASK 0x00020000 // HIF_1_EMPTY[17] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_SHFT 17 +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_MASK 0x00010000 // HIF_0_EMPTY[16] +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_SHFT 16 +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_MASK 0x00008000 // MDP_RXIOC3_QUEUE_EMPTY[15] +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_SHFT 15 +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_MASK 0x00000800 // MDP_RXIOC2_QUEUE_EMPTY[11] +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_SHFT 11 +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_MASK 0x00000400 // MDP_TXIOC2_QUEUE_EMPTY[10] +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_SHFT 10 +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_MASK 0x00000200 // SEC_TX2_QUEUE_EMPTY[9] +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_SHFT 9 +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_MASK 0x00000100 // MDP_TX2_QUEUE_EMPTY[8] +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_SHFT 8 + +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK 0x0FFF0000 // HIF0_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK 0x00000FFF // HIF0_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT 0 + + +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK 0x0FFF0000 // HIF1_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK 0x00000FFF // HIF1_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK 0x0FFF0000 // PLE_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK 0x00000FFF // PLE_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK 0x0FFF0000 // LMAC0_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK 0x00000FFF // LMAC0_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK 0x0FFF0000 // LMAC1_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK 0x00000FFF // LMAC1_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK 0x0FFF0000 // LMAC2_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK 0x00000FFF // LMAC2_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK 0x0FFF0000 // LMAC3_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK 0x00000FFF // LMAC3_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK 0x0FFF0000 // MDP_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK 0x00000FFF // MDP_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP2_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_MASK 0x0FFF0000 // MDP2_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP2_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_MASK 0x00000FFF // MDP2_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF2_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_MASK 0x0FFF0000 // HIF2_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF2_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_MASK 0x00000FFF // HIF2_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP3_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_MASK 0x0FFF0000 // MDP3_MAX_QUOTA[27..16] +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP3_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_MASK 0x00000FFF // MDP3_MIN_QUOTA[11..0] +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK 0x0FFF0000 // HIF0_SRC_CNT[27..16] +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK 0x00000FFF // HIF0_RSV_CNT[11..0] +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK 0x0FFF0000 // HIF1_SRC_CNT[27..16] +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK 0x00000FFF // HIF1_RSV_CNT[11..0] +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16] +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0] +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK 0x0FFF0000 // PLE_SRC_CNT[27..16] +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK 0x00000FFF // PLE_RSV_CNT[11..0] +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK 0x0FFF0000 // LMAC0_SRC_CNT[27..16] +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK 0x00000FFF // LMAC0_RSV_CNT[11..0] +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK 0x0FFF0000 // LMAC1_SRC_CNT[27..16] +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK 0x00000FFF // LMAC1_RSV_CNT[11..0] +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK 0x0FFF0000 // LMAC2_SRC_CNT[27..16] +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK 0x00000FFF // LMAC2_RSV_CNT[11..0] +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK 0x0FFF0000 // LMAC3_SRC_CNT[27..16] +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK 0x00000FFF // LMAC3_RSV_CNT[11..0] +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK 0x0FFF0000 // MDP_SRC_CNT[27..16] +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK 0x00000FFF // MDP_RSV_CNT[11..0] +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_ADDR WF_PSE_TOP_MDP2_PG_INFO_ADDR +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_MASK 0x0FFF0000 // MDP2_SRC_CNT[27..16] +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_ADDR WF_PSE_TOP_MDP2_PG_INFO_ADDR +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_MASK 0x00000FFF // MDP2_RSV_CNT[11..0] +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_ADDR WF_PSE_TOP_HIF2_PG_INFO_ADDR +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_MASK 0x0FFF0000 // HIF2_SRC_CNT[27..16] +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_ADDR WF_PSE_TOP_HIF2_PG_INFO_ADDR +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_MASK 0x00000FFF // HIF2_RSV_CNT[11..0] +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_ADDR WF_PSE_TOP_MDP3_PG_INFO_ADDR +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_MASK 0x0FFF0000 // MDP3_SRC_CNT[27..16] +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_ADDR WF_PSE_TOP_MDP3_PG_INFO_ADDR +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_MASK 0x00000FFF // MDP3_RSV_CNT[11..0] +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31] +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31 +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24] +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24 + +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_ADDR WF_PSE_TOP_FL_QUE_CTRL_1_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_MASK 0x30000000 // Q_BUF_PID[29..28] +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT 28 + +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16] +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16 +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0] +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0 + +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_MASK 0x00FFF000 // QUEUE_PAGE_NUM[23..12] +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_SHFT 12 +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0] +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0 + +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16] +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16 +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0] +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0 + +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16] +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16 +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0] +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0 + +/* RXD */ +enum { + BMAC_GROUP_VLD_1 = 0x01, + BMAC_GROUP_VLD_2 = 0x02, + BMAC_GROUP_VLD_3 = 0x04, + BMAC_GROUP_VLD_4 = 0x08, + BMAC_GROUP_VLD_5 = 0x10, +}; + +// DW0 +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_DW 0 +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_ADDR 0 +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_MASK 0x0000ffff // 15- 0 +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_SHIFT 0 +#define WF_RX_DESCRIPTOR_PACKET_TYPE_DW 0 +#define WF_RX_DESCRIPTOR_PACKET_TYPE_ADDR 0 +#define WF_RX_DESCRIPTOR_PACKET_TYPE_MASK 0xf8000000 // 31-27 +#define WF_RX_DESCRIPTOR_PACKET_TYPE_SHIFT 27 +// DW1 +#define WF_RX_DESCRIPTOR_MLD_ID_DW 1 +#define WF_RX_DESCRIPTOR_MLD_ID_ADDR 4 +#define WF_RX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0 +#define WF_RX_DESCRIPTOR_MLD_ID_SHIFT 0 +#define WF_RX_DESCRIPTOR_GROUP_VLD_DW 1 +#define WF_RX_DESCRIPTOR_GROUP_VLD_ADDR 4 +#define WF_RX_DESCRIPTOR_GROUP_VLD_MASK 0x001f0000 // 20-16 +#define WF_RX_DESCRIPTOR_GROUP_VLD_SHIFT 16 +#define WF_RX_DESCRIPTOR_KID_DW 1 +#define WF_RX_DESCRIPTOR_KID_ADDR 4 +#define WF_RX_DESCRIPTOR_KID_MASK 0x00600000 // 22-21 +#define WF_RX_DESCRIPTOR_KID_SHIFT 21 +#define WF_RX_DESCRIPTOR_CM_DW 1 +#define WF_RX_DESCRIPTOR_CM_ADDR 4 +#define WF_RX_DESCRIPTOR_CM_MASK 0x00800000 // 23-23 +#define WF_RX_DESCRIPTOR_CM_SHIFT 23 +#define WF_RX_DESCRIPTOR_CLM_DW 1 +#define WF_RX_DESCRIPTOR_CLM_ADDR 4 +#define WF_RX_DESCRIPTOR_CLM_MASK 0x01000000 // 24-24 +#define WF_RX_DESCRIPTOR_CLM_SHIFT 24 +#define WF_RX_DESCRIPTOR_I_DW 1 +#define WF_RX_DESCRIPTOR_I_ADDR 4 +#define WF_RX_DESCRIPTOR_I_MASK 0x02000000 // 25-25 +#define WF_RX_DESCRIPTOR_I_SHIFT 25 +#define WF_RX_DESCRIPTOR_T_DW 1 +#define WF_RX_DESCRIPTOR_T_ADDR 4 +#define WF_RX_DESCRIPTOR_T_MASK 0x04000000 // 26-26 +#define WF_RX_DESCRIPTOR_T_SHIFT 26 +#define WF_RX_DESCRIPTOR_BN_DW 1 +#define WF_RX_DESCRIPTOR_BN_ADDR 4 +#define WF_RX_DESCRIPTOR_BN_MASK 0x18000000 // 28-27 +#define WF_RX_DESCRIPTOR_BN_SHIFT 27 +#define WF_RX_DESCRIPTOR_BIPN_FAIL_DW 1 +#define WF_RX_DESCRIPTOR_BIPN_FAIL_ADDR 4 +#define WF_RX_DESCRIPTOR_BIPN_FAIL_MASK 0x20000000 // 29-29 +#define WF_RX_DESCRIPTOR_BIPN_FAIL_SHIFT 29 +// DW2 +#define WF_RX_DESCRIPTOR_BSSID_DW 2 +#define WF_RX_DESCRIPTOR_BSSID_ADDR 8 +#define WF_RX_DESCRIPTOR_BSSID_MASK 0x0000003f // 5- 0 +#define WF_RX_DESCRIPTOR_BSSID_SHIFT 0 +#define WF_RX_DESCRIPTOR_H_DW 2 +#define WF_RX_DESCRIPTOR_H_ADDR 8 +#define WF_RX_DESCRIPTOR_H_MASK 0x00000080 // 7- 7 +#define WF_RX_DESCRIPTOR_H_SHIFT 7 +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_DW 2 +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_ADDR 8 +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_MASK 0x00001f00 // 12- 8 +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_SHIFT 8 +#define WF_RX_DESCRIPTOR_HO_DW 2 +#define WF_RX_DESCRIPTOR_HO_ADDR 8 +#define WF_RX_DESCRIPTOR_HO_MASK 0x0000e000 // 15-13 +#define WF_RX_DESCRIPTOR_HO_SHIFT 13 +#define WF_RX_DESCRIPTOR_SEC_MODE_DW 2 +#define WF_RX_DESCRIPTOR_SEC_MODE_ADDR 8 +#define WF_RX_DESCRIPTOR_SEC_MODE_MASK 0x001f0000 // 20-16 +#define WF_RX_DESCRIPTOR_SEC_MODE_SHIFT 16 +#define WF_RX_DESCRIPTOR_MUBAR_DW 2 +#define WF_RX_DESCRIPTOR_MUBAR_ADDR 8 +#define WF_RX_DESCRIPTOR_MUBAR_MASK 0x00200000 // 21-21 +#define WF_RX_DESCRIPTOR_MUBAR_SHIFT 21 +#define WF_RX_DESCRIPTOR_SWBIT_DW 2 +#define WF_RX_DESCRIPTOR_SWBIT_ADDR 8 +#define WF_RX_DESCRIPTOR_SWBIT_MASK 0x00400000 // 22-22 +#define WF_RX_DESCRIPTOR_SWBIT_SHIFT 22 +#define WF_RX_DESCRIPTOR_DAF_DW 2 +#define WF_RX_DESCRIPTOR_DAF_ADDR 8 +#define WF_RX_DESCRIPTOR_DAF_MASK 0x00800000 // 23-23 +#define WF_RX_DESCRIPTOR_DAF_SHIFT 23 +#define WF_RX_DESCRIPTOR_EL_DW 2 +#define WF_RX_DESCRIPTOR_EL_ADDR 8 +#define WF_RX_DESCRIPTOR_EL_MASK 0x01000000 // 24-24 +#define WF_RX_DESCRIPTOR_EL_SHIFT 24 +#define WF_RX_DESCRIPTOR_HTF_DW 2 +#define WF_RX_DESCRIPTOR_HTF_ADDR 8 +#define WF_RX_DESCRIPTOR_HTF_MASK 0x02000000 // 25-25 +#define WF_RX_DESCRIPTOR_HTF_SHIFT 25 +#define WF_RX_DESCRIPTOR_INTF_DW 2 +#define WF_RX_DESCRIPTOR_INTF_ADDR 8 +#define WF_RX_DESCRIPTOR_INTF_MASK 0x04000000 // 26-26 +#define WF_RX_DESCRIPTOR_INTF_SHIFT 26 +#define WF_RX_DESCRIPTOR_FRAG_DW 2 +#define WF_RX_DESCRIPTOR_FRAG_ADDR 8 +#define WF_RX_DESCRIPTOR_FRAG_MASK 0x08000000 // 27-27 +#define WF_RX_DESCRIPTOR_FRAG_SHIFT 27 +#define WF_RX_DESCRIPTOR_NUL_DW 2 +#define WF_RX_DESCRIPTOR_NUL_ADDR 8 +#define WF_RX_DESCRIPTOR_NUL_MASK 0x10000000 // 28-28 +#define WF_RX_DESCRIPTOR_NUL_SHIFT 28 +#define WF_RX_DESCRIPTOR_NDATA_DW 2 +#define WF_RX_DESCRIPTOR_NDATA_ADDR 8 +#define WF_RX_DESCRIPTOR_NDATA_MASK 0x20000000 // 29-29 +#define WF_RX_DESCRIPTOR_NDATA_SHIFT 29 +#define WF_RX_DESCRIPTOR_NAMP_DW 2 +#define WF_RX_DESCRIPTOR_NAMP_ADDR 8 +#define WF_RX_DESCRIPTOR_NAMP_MASK 0x40000000 // 30-30 +#define WF_RX_DESCRIPTOR_NAMP_SHIFT 30 +#define WF_RX_DESCRIPTOR_BF_RPT_DW 2 +#define WF_RX_DESCRIPTOR_BF_RPT_ADDR 8 +#define WF_RX_DESCRIPTOR_BF_RPT_MASK 0x80000000 // 31-31 +#define WF_RX_DESCRIPTOR_BF_RPT_SHIFT 31 +// DW3 +#define WF_RX_DESCRIPTOR_RXV_SN_DW 3 +#define WF_RX_DESCRIPTOR_RXV_SN_ADDR 12 +#define WF_RX_DESCRIPTOR_RXV_SN_MASK 0x000000ff // 7- 0 +#define WF_RX_DESCRIPTOR_RXV_SN_SHIFT 0 +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_DW 3 +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_ADDR 12 +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_MASK 0x0000ff00 // 15- 8 +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_SHIFT 8 +#define WF_RX_DESCRIPTOR_A1_TYPE_DW 3 +#define WF_RX_DESCRIPTOR_A1_TYPE_ADDR 12 +#define WF_RX_DESCRIPTOR_A1_TYPE_MASK 0x00030000 // 17-16 +#define WF_RX_DESCRIPTOR_A1_TYPE_SHIFT 16 +#define WF_RX_DESCRIPTOR_HTC_DW 3 +#define WF_RX_DESCRIPTOR_HTC_ADDR 12 +#define WF_RX_DESCRIPTOR_HTC_MASK 0x00040000 // 18-18 +#define WF_RX_DESCRIPTOR_HTC_SHIFT 18 +#define WF_RX_DESCRIPTOR_TCL_DW 3 +#define WF_RX_DESCRIPTOR_TCL_ADDR 12 +#define WF_RX_DESCRIPTOR_TCL_MASK 0x00080000 // 19-19 +#define WF_RX_DESCRIPTOR_TCL_SHIFT 19 +#define WF_RX_DESCRIPTOR_BBM_DW 3 +#define WF_RX_DESCRIPTOR_BBM_ADDR 12 +#define WF_RX_DESCRIPTOR_BBM_MASK 0x00100000 // 20-20 +#define WF_RX_DESCRIPTOR_BBM_SHIFT 20 +#define WF_RX_DESCRIPTOR_BU_DW 3 +#define WF_RX_DESCRIPTOR_BU_ADDR 12 +#define WF_RX_DESCRIPTOR_BU_MASK 0x00200000 // 21-21 +#define WF_RX_DESCRIPTOR_BU_SHIFT 21 +#define WF_RX_DESCRIPTOR_CO_ANT_DW 3 +#define WF_RX_DESCRIPTOR_CO_ANT_ADDR 12 +#define WF_RX_DESCRIPTOR_CO_ANT_MASK 0x00400000 // 22-22 +#define WF_RX_DESCRIPTOR_CO_ANT_SHIFT 22 +#define WF_RX_DESCRIPTOR_BF_CQI_DW 3 +#define WF_RX_DESCRIPTOR_BF_CQI_ADDR 12 +#define WF_RX_DESCRIPTOR_BF_CQI_MASK 0x00800000 // 23-23 +#define WF_RX_DESCRIPTOR_BF_CQI_SHIFT 23 +#define WF_RX_DESCRIPTOR_FC_DW 3 +#define WF_RX_DESCRIPTOR_FC_ADDR 12 +#define WF_RX_DESCRIPTOR_FC_MASK 0x01000000 // 24-24 +#define WF_RX_DESCRIPTOR_FC_SHIFT 24 +#define WF_RX_DESCRIPTOR_VLAN_DW 3 +#define WF_RX_DESCRIPTOR_VLAN_ADDR 12 +#define WF_RX_DESCRIPTOR_VLAN_MASK 0x80000000 // 31-31 +#define WF_RX_DESCRIPTOR_VLAN_SHIFT 31 +// DW4 +#define WF_RX_DESCRIPTOR_PF_DW 4 +#define WF_RX_DESCRIPTOR_PF_ADDR 16 +#define WF_RX_DESCRIPTOR_PF_MASK 0x00000003 // 1- 0 +#define WF_RX_DESCRIPTOR_PF_SHIFT 0 +#define WF_RX_DESCRIPTOR_MAC_DW 4 +#define WF_RX_DESCRIPTOR_MAC_ADDR 16 +#define WF_RX_DESCRIPTOR_MAC_MASK 0x00000004 // 2- 2 +#define WF_RX_DESCRIPTOR_MAC_SHIFT 2 +#define WF_RX_DESCRIPTOR_TID_DW 4 +#define WF_RX_DESCRIPTOR_TID_ADDR 16 +#define WF_RX_DESCRIPTOR_TID_MASK 0x00000078 // 6- 3 +#define WF_RX_DESCRIPTOR_TID_SHIFT 3 +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 4 +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 16 +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x00003f80 // 13- 7 +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 7 +#define WF_RX_DESCRIPTOR_IP_DW 4 +#define WF_RX_DESCRIPTOR_IP_ADDR 16 +#define WF_RX_DESCRIPTOR_IP_MASK 0x00004000 // 14-14 +#define WF_RX_DESCRIPTOR_IP_SHIFT 14 +#define WF_RX_DESCRIPTOR_UT_DW 4 +#define WF_RX_DESCRIPTOR_UT_ADDR 16 +#define WF_RX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15 +#define WF_RX_DESCRIPTOR_UT_SHIFT 15 +#define WF_RX_DESCRIPTOR_PSE_FID_DW 4 +#define WF_RX_DESCRIPTOR_PSE_FID_ADDR 16 +#define WF_RX_DESCRIPTOR_PSE_FID_MASK 0x0fff0000 // 27-16 +#define WF_RX_DESCRIPTOR_PSE_FID_SHIFT 16 +// DW5 +// DW6 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__DW 6 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__ADDR 24 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__SHIFT 0 +// DW7 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__DW 7 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__ADDR 28 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__MASK 0x00000003 // 1- 0 +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__SHIFT 0 +#define WF_RX_DESCRIPTOR_DP_DW 7 +#define WF_RX_DESCRIPTOR_DP_ADDR 28 +#define WF_RX_DESCRIPTOR_DP_MASK 0x00080000 // 19-19 +#define WF_RX_DESCRIPTOR_DP_SHIFT 19 +#define WF_RX_DESCRIPTOR_CLS_DW 7 +#define WF_RX_DESCRIPTOR_CLS_ADDR 28 +#define WF_RX_DESCRIPTOR_CLS_MASK 0x00100000 // 20-20 +#define WF_RX_DESCRIPTOR_CLS_SHIFT 20 +#define WF_RX_DESCRIPTOR_OFLD_DW 7 +#define WF_RX_DESCRIPTOR_OFLD_ADDR 28 +#define WF_RX_DESCRIPTOR_OFLD_MASK 0x00600000 // 22-21 +#define WF_RX_DESCRIPTOR_OFLD_SHIFT 21 +#define WF_RX_DESCRIPTOR_MGC_DW 7 +#define WF_RX_DESCRIPTOR_MGC_ADDR 28 +#define WF_RX_DESCRIPTOR_MGC_MASK 0x00800000 // 23-23 +#define WF_RX_DESCRIPTOR_MGC_SHIFT 23 +#define WF_RX_DESCRIPTOR_WOL_DW 7 +#define WF_RX_DESCRIPTOR_WOL_ADDR 28 +#define WF_RX_DESCRIPTOR_WOL_MASK 0x1f000000 // 28-24 +#define WF_RX_DESCRIPTOR_WOL_SHIFT 24 +#define WF_RX_DESCRIPTOR_PF_MODE_DW 7 +#define WF_RX_DESCRIPTOR_PF_MODE_ADDR 28 +#define WF_RX_DESCRIPTOR_PF_MODE_MASK 0x20000000 // 29-29 +#define WF_RX_DESCRIPTOR_PF_MODE_SHIFT 29 +#define WF_RX_DESCRIPTOR_PF_STS_DW 7 +#define WF_RX_DESCRIPTOR_PF_STS_ADDR 28 +#define WF_RX_DESCRIPTOR_PF_STS_MASK 0xc0000000 // 31-30 +#define WF_RX_DESCRIPTOR_PF_STS_SHIFT 30 +// DW8 +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_DW 8 +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_ADDR 32 +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_MASK 0x0000ffff // 15- 0 +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_SHIFT 0 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__DW 8 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__ADDR 32 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__MASK 0xffff0000 // 31-16 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__SHIFT 16 +// DW9 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__DW 9 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__ADDR 36 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__SHIFT 0 +// DW10 +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_DW 10 +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_ADDR 40 +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_MASK 0x0000000f // 3- 0 +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_SHIFT 0 +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_DW 10 +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_ADDR 40 +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_MASK 0x0000fff0 // 15- 4 +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_SHIFT 4 +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_DW 10 +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_ADDR 40 +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_MASK 0xffff0000 // 31-16 +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_SHIFT 16 +// DW11 +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_DW 11 +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_ADDR 44 +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_SHIFT 0 +// DW12 +#define WF_RX_DESCRIPTOR_PN_31_0__DW 12 +#define WF_RX_DESCRIPTOR_PN_31_0__ADDR 48 +#define WF_RX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_PN_31_0__SHIFT 0 +// DW13 +#define WF_RX_DESCRIPTOR_PN_63_32__DW 13 +#define WF_RX_DESCRIPTOR_PN_63_32__ADDR 52 +#define WF_RX_DESCRIPTOR_PN_63_32__MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_PN_63_32__SHIFT 0 +// DW14 +#define WF_RX_DESCRIPTOR_PN_95_64__DW 14 +#define WF_RX_DESCRIPTOR_PN_95_64__ADDR 56 +#define WF_RX_DESCRIPTOR_PN_95_64__MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_PN_95_64__SHIFT 0 +// DW15 +#define WF_RX_DESCRIPTOR_PN_127_96__DW 15 +#define WF_RX_DESCRIPTOR_PN_127_96__ADDR 60 +#define WF_RX_DESCRIPTOR_PN_127_96__MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_PN_127_96__SHIFT 0 +// DW16 +#define WF_RX_DESCRIPTOR_TIMESTAMP_DW 16 +#define WF_RX_DESCRIPTOR_TIMESTAMP_ADDR 64 +#define WF_RX_DESCRIPTOR_TIMESTAMP_MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_TIMESTAMP_SHIFT 0 +// DW17 +#define WF_RX_DESCRIPTOR_CRC_DW 17 +#define WF_RX_DESCRIPTOR_CRC_ADDR 68 +#define WF_RX_DESCRIPTOR_CRC_MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_CRC_SHIFT 0 +// DW18 +// DW19 +// DW20 +#define WF_RX_DESCRIPTOR_P_RXV_DW 20 +#define WF_RX_DESCRIPTOR_P_RXV_ADDR 80 +#define WF_RX_DESCRIPTOR_P_RXV_MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_P_RXV_SHIFT 0 +// DW21 +// DO NOT process repeat field(p_rxv) +// DW22 +#define WF_RX_DESCRIPTOR_DBW_DW 22 +#define WF_RX_DESCRIPTOR_DBW_ADDR 88 +#define WF_RX_DESCRIPTOR_DBW_MASK 0x00000007 // 2- 0 +#define WF_RX_DESCRIPTOR_DBW_SHIFT 0 +#define WF_RX_DESCRIPTOR_GI_DW 22 +#define WF_RX_DESCRIPTOR_GI_ADDR 88 +#define WF_RX_DESCRIPTOR_GI_MASK 0x00000018 // 4- 3 +#define WF_RX_DESCRIPTOR_GI_SHIFT 3 +#define WF_RX_DESCRIPTOR_DCM_DW 22 +#define WF_RX_DESCRIPTOR_DCM_ADDR 88 +#define WF_RX_DESCRIPTOR_DCM_MASK 0x00000020 // 5- 5 +#define WF_RX_DESCRIPTOR_DCM_SHIFT 5 +#define WF_RX_DESCRIPTOR_NUM_RX_DW 22 +#define WF_RX_DESCRIPTOR_NUM_RX_ADDR 88 +#define WF_RX_DESCRIPTOR_NUM_RX_MASK 0x000001c0 // 8- 6 +#define WF_RX_DESCRIPTOR_NUM_RX_SHIFT 6 +#define WF_RX_DESCRIPTOR_STBC_DW 22 +#define WF_RX_DESCRIPTOR_STBC_ADDR 88 +#define WF_RX_DESCRIPTOR_STBC_MASK 0x00000600 // 10- 9 +#define WF_RX_DESCRIPTOR_STBC_SHIFT 9 +#define WF_RX_DESCRIPTOR_TX_MODE_DW 22 +#define WF_RX_DESCRIPTOR_TX_MODE_ADDR 88 +#define WF_RX_DESCRIPTOR_TX_MODE_MASK 0x00007800 // 14-11 +#define WF_RX_DESCRIPTOR_TX_MODE_SHIFT 11 +// DW23 +#define WF_RX_DESCRIPTOR_RCPI_DW 23 +#define WF_RX_DESCRIPTOR_RCPI_ADDR 92 +#define WF_RX_DESCRIPTOR_RCPI_MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_RCPI_SHIFT 0 +// DW24 +#define WF_RX_DESCRIPTOR_C_RXV_DW 24 +#define WF_RX_DESCRIPTOR_C_RXV_ADDR 96 +#define WF_RX_DESCRIPTOR_C_RXV_MASK 0xffffffff // 31- 0 +#define WF_RX_DESCRIPTOR_C_RXV_SHIFT 0 +// DW25 +// DO NOT process repeat field(c_rxv) +// DW26 +// DO NOT process repeat field(c_rxv) +// DW27 +// DO NOT process repeat field(c_rxv) +// DW28 +// DO NOT process repeat field(c_rxv) +// DW29 +// DO NOT process repeat field(c_rxv) +// DW30 +// DO NOT process repeat field(c_rxv) +// DW31 +// DO NOT process repeat field(c_rxv) +// DW32 +// DO NOT process repeat field(c_rxv) +// DW33 +// DO NOT process repeat field(c_rxv) +// DW34 +// DO NOT process repeat field(c_rxv) +// DW35 +// DO NOT process repeat field(c_rxv) +// DW36 +// DO NOT process repeat field(c_rxv) +// DW37 +// DO NOT process repeat field(c_rxv) +// DW38 +// DO NOT process repeat field(c_rxv) +// DW39 +// DO NOT process repeat field(c_rxv) +// DW40 +// DO NOT process repeat field(c_rxv) +// DW41 +// DO NOT process repeat field(c_rxv) +// DW42 +// DO NOT process repeat field(c_rxv) +// DW43 +// DO NOT process repeat field(c_rxv) +// DW44 +// DO NOT process repeat field(c_rxv) +// DW45 +// DO NOT process repeat field(c_rxv) +// DW46 +// DW47 + +/* TXD */ +// DW0 +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_DW 0 +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_ADDR 0 +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_MASK 0x0000ffff // 15- 0 +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_SHIFT 0 +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 0 +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 0 +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x007f0000 // 22-16 +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 16 +#define WF_TX_DESCRIPTOR_PKT_FT_DW 0 +#define WF_TX_DESCRIPTOR_PKT_FT_ADDR 0 +#define WF_TX_DESCRIPTOR_PKT_FT_MASK 0x01800000 // 24-23 +#define WF_TX_DESCRIPTOR_PKT_FT_SHIFT 23 +#define WF_TX_DESCRIPTOR_Q_IDX_DW 0 +#define WF_TX_DESCRIPTOR_Q_IDX_ADDR 0 +#define WF_TX_DESCRIPTOR_Q_IDX_MASK 0xfe000000 // 31-25 +#define WF_TX_DESCRIPTOR_Q_IDX_SHIFT 25 +// DW1 +#define WF_TX_DESCRIPTOR_MLD_ID_DW 1 +#define WF_TX_DESCRIPTOR_MLD_ID_ADDR 4 +#define WF_TX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0 +#define WF_TX_DESCRIPTOR_MLD_ID_SHIFT 0 +#define WF_TX_DESCRIPTOR_TGID_DW 1 +#define WF_TX_DESCRIPTOR_TGID_ADDR 4 +#define WF_TX_DESCRIPTOR_TGID_MASK 0x00003000 // 13-12 +#define WF_TX_DESCRIPTOR_TGID_SHIFT 12 +#define WF_TX_DESCRIPTOR_HF_DW 1 +#define WF_TX_DESCRIPTOR_HF_ADDR 4 +#define WF_TX_DESCRIPTOR_HF_MASK 0x0000c000 // 15-14 +#define WF_TX_DESCRIPTOR_HF_SHIFT 14 +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_DW 1 +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_ADDR 4 +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_MASK 0x001f0000 // 20-16 +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_SHIFT 16 +#define WF_TX_DESCRIPTOR_MRD_DW 1 +#define WF_TX_DESCRIPTOR_MRD_ADDR 4 +#define WF_TX_DESCRIPTOR_MRD_MASK 0x00010000 // 16-16 +#define WF_TX_DESCRIPTOR_MRD_SHIFT 16 +#define WF_TX_DESCRIPTOR_EOSP_DW 1 +#define WF_TX_DESCRIPTOR_EOSP_ADDR 4 +#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17 +#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17 +#define WF_TX_DESCRIPTOR_EOSP_DW 1 +#define WF_TX_DESCRIPTOR_EOSP_ADDR 4 +#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17 +#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17 +#define WF_TX_DESCRIPTOR_AMS_DW 1 +#define WF_TX_DESCRIPTOR_AMS_ADDR 4 +#define WF_TX_DESCRIPTOR_AMS_MASK 0x00040000 // 18-18 +#define WF_TX_DESCRIPTOR_AMS_SHIFT 18 +#define WF_TX_DESCRIPTOR_RMVL_DW 1 +#define WF_TX_DESCRIPTOR_RMVL_ADDR 4 +#define WF_TX_DESCRIPTOR_RMVL_MASK 0x00040000 // 18-18 +#define WF_TX_DESCRIPTOR_RMVL_SHIFT 18 +#define WF_TX_DESCRIPTOR_VLAN_DW 1 +#define WF_TX_DESCRIPTOR_VLAN_ADDR 4 +#define WF_TX_DESCRIPTOR_VLAN_MASK 0x00080000 // 19-19 +#define WF_TX_DESCRIPTOR_VLAN_SHIFT 19 +#define WF_TX_DESCRIPTOR_ETYP_DW 1 +#define WF_TX_DESCRIPTOR_ETYP_ADDR 4 +#define WF_TX_DESCRIPTOR_ETYP_MASK 0x00100000 // 20-20 +#define WF_TX_DESCRIPTOR_ETYP_SHIFT 20 +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_DW 1 +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_ADDR 4 +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_MASK 0x01e00000 // 24-21 +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_SHIFT 21 +#define WF_TX_DESCRIPTOR_OM_DW 1 +#define WF_TX_DESCRIPTOR_OM_ADDR 4 +#define WF_TX_DESCRIPTOR_OM_MASK 0x7e000000 // 30-25 +#define WF_TX_DESCRIPTOR_OM_SHIFT 25 +#define WF_TX_DESCRIPTOR_FR_DW 1 +#define WF_TX_DESCRIPTOR_FR_ADDR 4 +#define WF_TX_DESCRIPTOR_FR_MASK 0x80000000 // 31-31 +#define WF_TX_DESCRIPTOR_FR_SHIFT 31 +// DW2 +#define WF_TX_DESCRIPTOR_SUBTYPE_DW 2 +#define WF_TX_DESCRIPTOR_SUBTYPE_ADDR 8 +#define WF_TX_DESCRIPTOR_SUBTYPE_MASK 0x0000000f // 3- 0 +#define WF_TX_DESCRIPTOR_SUBTYPE_SHIFT 0 +#define WF_TX_DESCRIPTOR_FTYPE_DW 2 +#define WF_TX_DESCRIPTOR_FTYPE_ADDR 8 +#define WF_TX_DESCRIPTOR_FTYPE_MASK 0x00000030 // 5- 4 +#define WF_TX_DESCRIPTOR_FTYPE_SHIFT 4 +#define WF_TX_DESCRIPTOR_BF_TYPE_DW 2 +#define WF_TX_DESCRIPTOR_BF_TYPE_ADDR 8 +#define WF_TX_DESCRIPTOR_BF_TYPE_MASK 0x000000c0 // 7- 6 +#define WF_TX_DESCRIPTOR_BF_TYPE_SHIFT 6 +#define WF_TX_DESCRIPTOR_OM_MAP_DW 2 +#define WF_TX_DESCRIPTOR_OM_MAP_ADDR 8 +#define WF_TX_DESCRIPTOR_OM_MAP_MASK 0x00000100 // 8- 8 +#define WF_TX_DESCRIPTOR_OM_MAP_SHIFT 8 +#define WF_TX_DESCRIPTOR_RTS_DW 2 +#define WF_TX_DESCRIPTOR_RTS_ADDR 8 +#define WF_TX_DESCRIPTOR_RTS_MASK 0x00000200 // 9- 9 +#define WF_TX_DESCRIPTOR_RTS_SHIFT 9 +#define WF_TX_DESCRIPTOR_HEADER_PADDING_DW 2 +#define WF_TX_DESCRIPTOR_HEADER_PADDING_ADDR 8 +#define WF_TX_DESCRIPTOR_HEADER_PADDING_MASK 0x00000c00 // 11-10 +#define WF_TX_DESCRIPTOR_HEADER_PADDING_SHIFT 10 +#define WF_TX_DESCRIPTOR_DU_DW 2 +#define WF_TX_DESCRIPTOR_DU_ADDR 8 +#define WF_TX_DESCRIPTOR_DU_MASK 0x00001000 // 12-12 +#define WF_TX_DESCRIPTOR_DU_SHIFT 12 +#define WF_TX_DESCRIPTOR_HE_DW 2 +#define WF_TX_DESCRIPTOR_HE_ADDR 8 +#define WF_TX_DESCRIPTOR_HE_MASK 0x00002000 // 13-13 +#define WF_TX_DESCRIPTOR_HE_SHIFT 13 +#define WF_TX_DESCRIPTOR_FRAG_DW 2 +#define WF_TX_DESCRIPTOR_FRAG_ADDR 8 +#define WF_TX_DESCRIPTOR_FRAG_MASK 0x0000c000 // 15-14 +#define WF_TX_DESCRIPTOR_FRAG_SHIFT 14 +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_DW 2 +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_ADDR 8 +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_MASK 0x03ff0000 // 25-16 +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_SHIFT 16 +#define WF_TX_DESCRIPTOR_POWER_OFFSET_DW 2 +#define WF_TX_DESCRIPTOR_POWER_OFFSET_ADDR 8 +#define WF_TX_DESCRIPTOR_POWER_OFFSET_MASK 0xfc000000 // 31-26 +#define WF_TX_DESCRIPTOR_POWER_OFFSET_SHIFT 26 +// DW3 +#define WF_TX_DESCRIPTOR_NA_DW 3 +#define WF_TX_DESCRIPTOR_NA_ADDR 12 +#define WF_TX_DESCRIPTOR_NA_MASK 0x00000001 // 0- 0 +#define WF_TX_DESCRIPTOR_NA_SHIFT 0 +#define WF_TX_DESCRIPTOR_PF_DW 3 +#define WF_TX_DESCRIPTOR_PF_ADDR 12 +#define WF_TX_DESCRIPTOR_PF_MASK 0x00000002 // 1- 1 +#define WF_TX_DESCRIPTOR_PF_SHIFT 1 +#define WF_TX_DESCRIPTOR_EMRD_DW 3 +#define WF_TX_DESCRIPTOR_EMRD_ADDR 12 +#define WF_TX_DESCRIPTOR_EMRD_MASK 0x00000004 // 2- 2 +#define WF_TX_DESCRIPTOR_EMRD_SHIFT 2 +#define WF_TX_DESCRIPTOR_EEOSP_DW 3 +#define WF_TX_DESCRIPTOR_EEOSP_ADDR 12 +#define WF_TX_DESCRIPTOR_EEOSP_MASK 0x00000008 // 3- 3 +#define WF_TX_DESCRIPTOR_EEOSP_SHIFT 3 +#define WF_TX_DESCRIPTOR_BM_DW 3 +#define WF_TX_DESCRIPTOR_BM_ADDR 12 +#define WF_TX_DESCRIPTOR_BM_MASK 0x00000010 // 4- 4 +#define WF_TX_DESCRIPTOR_BM_SHIFT 4 +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_DW 3 +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_ADDR 12 +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_MASK 0x00000020 // 5- 5 +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_SHIFT 5 +#define WF_TX_DESCRIPTOR_TX_COUNT_DW 3 +#define WF_TX_DESCRIPTOR_TX_COUNT_ADDR 12 +#define WF_TX_DESCRIPTOR_TX_COUNT_MASK 0x000007c0 // 10- 6 +#define WF_TX_DESCRIPTOR_TX_COUNT_SHIFT 6 +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_DW 3 +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_ADDR 12 +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_MASK 0x0000f800 // 15-11 +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_SHIFT 11 +#define WF_TX_DESCRIPTOR_SN_DW 3 +#define WF_TX_DESCRIPTOR_SN_ADDR 12 +#define WF_TX_DESCRIPTOR_SN_MASK 0x0fff0000 // 27-16 +#define WF_TX_DESCRIPTOR_SN_SHIFT 16 +#define WF_TX_DESCRIPTOR_BA_DIS_DW 3 +#define WF_TX_DESCRIPTOR_BA_DIS_ADDR 12 +#define WF_TX_DESCRIPTOR_BA_DIS_MASK 0x10000000 // 28-28 +#define WF_TX_DESCRIPTOR_BA_DIS_SHIFT 28 +#define WF_TX_DESCRIPTOR_PM_DW 3 +#define WF_TX_DESCRIPTOR_PM_ADDR 12 +#define WF_TX_DESCRIPTOR_PM_MASK 0x20000000 // 29-29 +#define WF_TX_DESCRIPTOR_PM_SHIFT 29 +#define WF_TX_DESCRIPTOR_PN_VLD_DW 3 +#define WF_TX_DESCRIPTOR_PN_VLD_ADDR 12 +#define WF_TX_DESCRIPTOR_PN_VLD_MASK 0x40000000 // 30-30 +#define WF_TX_DESCRIPTOR_PN_VLD_SHIFT 30 +#define WF_TX_DESCRIPTOR_SN_VLD_DW 3 +#define WF_TX_DESCRIPTOR_SN_VLD_ADDR 12 +#define WF_TX_DESCRIPTOR_SN_VLD_MASK 0x80000000 // 31-31 +#define WF_TX_DESCRIPTOR_SN_VLD_SHIFT 31 +// DW4 +#define WF_TX_DESCRIPTOR_PN_31_0__DW 4 +#define WF_TX_DESCRIPTOR_PN_31_0__ADDR 16 +#define WF_TX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_PN_31_0__SHIFT 0 +// DW5 +#define WF_TX_DESCRIPTOR_PID_DW 5 +#define WF_TX_DESCRIPTOR_PID_ADDR 20 +#define WF_TX_DESCRIPTOR_PID_MASK 0x000000ff // 7- 0 +#define WF_TX_DESCRIPTOR_PID_SHIFT 0 +#define WF_TX_DESCRIPTOR_TXSFM_DW 5 +#define WF_TX_DESCRIPTOR_TXSFM_ADDR 20 +#define WF_TX_DESCRIPTOR_TXSFM_MASK 0x00000100 // 8- 8 +#define WF_TX_DESCRIPTOR_TXSFM_SHIFT 8 +#define WF_TX_DESCRIPTOR_TXS2M_DW 5 +#define WF_TX_DESCRIPTOR_TXS2M_ADDR 20 +#define WF_TX_DESCRIPTOR_TXS2M_MASK 0x00000200 // 9- 9 +#define WF_TX_DESCRIPTOR_TXS2M_SHIFT 9 +#define WF_TX_DESCRIPTOR_TXS2H_DW 5 +#define WF_TX_DESCRIPTOR_TXS2H_ADDR 20 +#define WF_TX_DESCRIPTOR_TXS2H_MASK 0x00000400 // 10-10 +#define WF_TX_DESCRIPTOR_TXS2H_SHIFT 10 +#define WF_TX_DESCRIPTOR_FBCZ_DW 5 +#define WF_TX_DESCRIPTOR_FBCZ_ADDR 20 +#define WF_TX_DESCRIPTOR_FBCZ_MASK 0x00001000 // 12-12 +#define WF_TX_DESCRIPTOR_FBCZ_SHIFT 12 +#define WF_TX_DESCRIPTOR_BYPASS_RBB_DW 5 +#define WF_TX_DESCRIPTOR_BYPASS_RBB_ADDR 20 +#define WF_TX_DESCRIPTOR_BYPASS_RBB_MASK 0x00002000 // 13-13 +#define WF_TX_DESCRIPTOR_BYPASS_RBB_SHIFT 13 +#define WF_TX_DESCRIPTOR_BYPASS_TBB_DW 5 +#define WF_TX_DESCRIPTOR_BYPASS_TBB_ADDR 20 +#define WF_TX_DESCRIPTOR_BYPASS_TBB_MASK 0x00004000 // 14-14 +#define WF_TX_DESCRIPTOR_BYPASS_TBB_SHIFT 14 +#define WF_TX_DESCRIPTOR_FL_DW 5 +#define WF_TX_DESCRIPTOR_FL_ADDR 20 +#define WF_TX_DESCRIPTOR_FL_MASK 0x00008000 // 15-15 +#define WF_TX_DESCRIPTOR_FL_SHIFT 15 +#define WF_TX_DESCRIPTOR_PN_47_32__DW 5 +#define WF_TX_DESCRIPTOR_PN_47_32__ADDR 20 +#define WF_TX_DESCRIPTOR_PN_47_32__MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_PN_47_32__SHIFT 16 +// DW6 +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_DW 6 +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_ADDR 24 +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_MASK 0x00000002 // 1- 1 +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_SHIFT 1 +#define WF_TX_DESCRIPTOR_DAS_DW 6 +#define WF_TX_DESCRIPTOR_DAS_ADDR 24 +#define WF_TX_DESCRIPTOR_DAS_MASK 0x00000004 // 2- 2 +#define WF_TX_DESCRIPTOR_DAS_SHIFT 2 +#define WF_TX_DESCRIPTOR_DIS_MAT_DW 6 +#define WF_TX_DESCRIPTOR_DIS_MAT_ADDR 24 +#define WF_TX_DESCRIPTOR_DIS_MAT_MASK 0x00000008 // 3- 3 +#define WF_TX_DESCRIPTOR_DIS_MAT_SHIFT 3 +#define WF_TX_DESCRIPTOR_MSDU_COUNT_DW 6 +#define WF_TX_DESCRIPTOR_MSDU_COUNT_ADDR 24 +#define WF_TX_DESCRIPTOR_MSDU_COUNT_MASK 0x000003f0 // 9- 4 +#define WF_TX_DESCRIPTOR_MSDU_COUNT_SHIFT 4 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_DW 6 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_ADDR 24 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_MASK 0x00007c00 // 14-10 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_SHIFT 10 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_DW 6 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_ADDR 24 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_MASK 0x00008000 // 15-15 +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_SHIFT 15 +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_DW 6 +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_ADDR 24 +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_MASK 0x003f0000 // 21-16 +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_SHIFT 16 +#define WF_TX_DESCRIPTOR_BW_DW 6 +#define WF_TX_DESCRIPTOR_BW_ADDR 24 +#define WF_TX_DESCRIPTOR_BW_MASK 0x03c00000 // 25-22 +#define WF_TX_DESCRIPTOR_BW_SHIFT 22 +#define WF_TX_DESCRIPTOR_VTA_DW 6 +#define WF_TX_DESCRIPTOR_VTA_ADDR 24 +#define WF_TX_DESCRIPTOR_VTA_MASK 0x10000000 // 28-28 +#define WF_TX_DESCRIPTOR_VTA_SHIFT 28 +#define WF_TX_DESCRIPTOR_SRC_DW 6 +#define WF_TX_DESCRIPTOR_SRC_ADDR 24 +#define WF_TX_DESCRIPTOR_SRC_MASK 0xc0000000 // 31-30 +#define WF_TX_DESCRIPTOR_SRC_SHIFT 30 +// DW7 +#define WF_TX_DESCRIPTOR_SW_TX_TIME_DW 7 +#define WF_TX_DESCRIPTOR_SW_TX_TIME_ADDR 28 +#define WF_TX_DESCRIPTOR_SW_TX_TIME_MASK 0x000003ff // 9- 0 +#define WF_TX_DESCRIPTOR_SW_TX_TIME_SHIFT 0 +#define WF_TX_DESCRIPTOR_UT_DW 7 +#define WF_TX_DESCRIPTOR_UT_ADDR 28 +#define WF_TX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15 +#define WF_TX_DESCRIPTOR_UT_SHIFT 15 +#define WF_TX_DESCRIPTOR_CTXD_CNT_DW 7 +#define WF_TX_DESCRIPTOR_CTXD_CNT_ADDR 28 +#define WF_TX_DESCRIPTOR_CTXD_CNT_MASK 0x03c00000 // 25-22 +#define WF_TX_DESCRIPTOR_CTXD_CNT_SHIFT 22 +#define WF_TX_DESCRIPTOR_CTXD_DW 7 +#define WF_TX_DESCRIPTOR_CTXD_ADDR 28 +#define WF_TX_DESCRIPTOR_CTXD_MASK 0x04000000 // 26-26 +#define WF_TX_DESCRIPTOR_CTXD_SHIFT 26 +#define WF_TX_DESCRIPTOR_HM_DW 7 +#define WF_TX_DESCRIPTOR_HM_ADDR 28 +#define WF_TX_DESCRIPTOR_HM_MASK 0x08000000 // 27-27 +#define WF_TX_DESCRIPTOR_HM_SHIFT 27 +#define WF_TX_DESCRIPTOR_DP_DW 7 +#define WF_TX_DESCRIPTOR_DP_ADDR 28 +#define WF_TX_DESCRIPTOR_DP_MASK 0x10000000 // 28-28 +#define WF_TX_DESCRIPTOR_DP_SHIFT 28 +#define WF_TX_DESCRIPTOR_IP_DW 7 +#define WF_TX_DESCRIPTOR_IP_ADDR 28 +#define WF_TX_DESCRIPTOR_IP_MASK 0x20000000 // 29-29 +#define WF_TX_DESCRIPTOR_IP_SHIFT 29 +#define WF_TX_DESCRIPTOR_TXD_LEN_DW 7 +#define WF_TX_DESCRIPTOR_TXD_LEN_ADDR 28 +#define WF_TX_DESCRIPTOR_TXD_LEN_MASK 0xc0000000 // 31-30 +#define WF_TX_DESCRIPTOR_TXD_LEN_SHIFT 30 +// DW8 +#define WF_TX_DESCRIPTOR_MSDU0_DW 8 +#define WF_TX_DESCRIPTOR_MSDU0_ADDR 32 +#define WF_TX_DESCRIPTOR_MSDU0_MASK 0x0000ffff // 15- 0 +#define WF_TX_DESCRIPTOR_MSDU0_SHIFT 0 +#define WF_TX_DESCRIPTOR_MSDU1_DW 8 +#define WF_TX_DESCRIPTOR_MSDU1_ADDR 32 +#define WF_TX_DESCRIPTOR_MSDU1_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_MSDU1_SHIFT 16 +// DW9 +#define WF_TX_DESCRIPTOR_MSDU2_DW 9 +#define WF_TX_DESCRIPTOR_MSDU2_ADDR 36 +#define WF_TX_DESCRIPTOR_MSDU2_MASK 0x0000ffff // 15- 0 +#define WF_TX_DESCRIPTOR_MSDU2_SHIFT 0 +#define WF_TX_DESCRIPTOR_MSDU3_DW 9 +#define WF_TX_DESCRIPTOR_MSDU3_ADDR 36 +#define WF_TX_DESCRIPTOR_MSDU3_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_MSDU3_SHIFT 16 +// DW10 +#define WF_TX_DESCRIPTOR_TXP0_DW 10 +#define WF_TX_DESCRIPTOR_TXP0_ADDR 40 +#define WF_TX_DESCRIPTOR_TXP0_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP0_SHIFT 0 +// DW11 +// DO NOT process repeat field(txp[0]) +#define WF_TX_DESCRIPTOR_TXP1_DW 11 +#define WF_TX_DESCRIPTOR_TXP1_ADDR 44 +#define WF_TX_DESCRIPTOR_TXP1_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP1_SHIFT 16 +// DW12 +// DO NOT process repeat field(txp[1]) +// DW13 +#define WF_TX_DESCRIPTOR_TXP2_DW 13 +#define WF_TX_DESCRIPTOR_TXP2_ADDR 52 +#define WF_TX_DESCRIPTOR_TXP2_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP2_SHIFT 0 +// DW14 +// DO NOT process repeat field(txp[2]) +#define WF_TX_DESCRIPTOR_TXP3_DW 14 +#define WF_TX_DESCRIPTOR_TXP3_ADDR 56 +#define WF_TX_DESCRIPTOR_TXP3_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP3_SHIFT 16 +// DW15 +// DO NOT process repeat field(txp[3]) +// DW16 +#define WF_TX_DESCRIPTOR_MSDU4_DW 16 +#define WF_TX_DESCRIPTOR_MSDU4_ADDR 64 +#define WF_TX_DESCRIPTOR_MSDU4_MASK 0x0000ffff // 15- 0 +#define WF_TX_DESCRIPTOR_MSDU4_SHIFT 0 +#define WF_TX_DESCRIPTOR_MSDU5_DW 16 +#define WF_TX_DESCRIPTOR_MSDU5_ADDR 64 +#define WF_TX_DESCRIPTOR_MSDU5_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_MSDU5_SHIFT 16 +// DW17 +#define WF_TX_DESCRIPTOR_MSDU6_DW 17 +#define WF_TX_DESCRIPTOR_MSDU6_ADDR 68 +#define WF_TX_DESCRIPTOR_MSDU6_MASK 0x0000ffff // 15- 0 +#define WF_TX_DESCRIPTOR_MSDU6_SHIFT 0 +#define WF_TX_DESCRIPTOR_MSDU7_DW 17 +#define WF_TX_DESCRIPTOR_MSDU7_ADDR 68 +#define WF_TX_DESCRIPTOR_MSDU7_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_MSDU7_SHIFT 16 +// DW18 +#define WF_TX_DESCRIPTOR_TXP4_DW 18 +#define WF_TX_DESCRIPTOR_TXP4_ADDR 72 +#define WF_TX_DESCRIPTOR_TXP4_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP4_SHIFT 0 +// DW19 +// DO NOT process repeat field(txp[4]) +#define WF_TX_DESCRIPTOR_TXP5_DW 19 +#define WF_TX_DESCRIPTOR_TXP5_ADDR 76 +#define WF_TX_DESCRIPTOR_TXP5_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP5_SHIFT 16 +// DW20 +// DO NOT process repeat field(txp[5]) +// DW21 +#define WF_TX_DESCRIPTOR_TXP6_DW 21 +#define WF_TX_DESCRIPTOR_TXP6_ADDR 84 +#define WF_TX_DESCRIPTOR_TXP6_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP6_SHIFT 0 +// DW22 +// DO NOT process repeat field(txp[6]) +#define WF_TX_DESCRIPTOR_TXP7_DW 22 +#define WF_TX_DESCRIPTOR_TXP7_ADDR 88 +#define WF_TX_DESCRIPTOR_TXP7_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP7_SHIFT 16 +// DW23 +// DO NOT process repeat field(txp[7]) +// DW24 +#define WF_TX_DESCRIPTOR_TXP8_DW 24 +#define WF_TX_DESCRIPTOR_TXP8_ADDR 96 +#define WF_TX_DESCRIPTOR_TXP8_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP8_SHIFT 0 +// DW25 +// DO NOT process repeat field(txp[8]) +#define WF_TX_DESCRIPTOR_TXP9_DW 25 +#define WF_TX_DESCRIPTOR_TXP9_ADDR 100 +#define WF_TX_DESCRIPTOR_TXP9_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP9_SHIFT 16 +// DW26 +// DO NOT process repeat field(txp[9]) +// DW27 +#define WF_TX_DESCRIPTOR_TXP10_DW 27 +#define WF_TX_DESCRIPTOR_TXP10_ADDR 108 +#define WF_TX_DESCRIPTOR_TXP10_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP10_SHIFT 0 +// DW28 +// DO NOT process repeat field(txp[10]) +#define WF_TX_DESCRIPTOR_TXP11_DW 28 +#define WF_TX_DESCRIPTOR_TXP11_ADDR 112 +#define WF_TX_DESCRIPTOR_TXP11_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP11_SHIFT 16 +// DW29 +// DO NOT process repeat field(txp[11]) +// DW30 +#define WF_TX_DESCRIPTOR_TXP12_DW 30 +#define WF_TX_DESCRIPTOR_TXP12_ADDR 120 +#define WF_TX_DESCRIPTOR_TXP12_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP12_SHIFT 0 +// DW31 +// DO NOT process repeat field(txp[12]) +#define WF_TX_DESCRIPTOR_TXP13_DW 31 +#define WF_TX_DESCRIPTOR_TXP13_ADDR 124 +#define WF_TX_DESCRIPTOR_TXP13_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP13_SHIFT 16 +// DW32 +// DO NOT process repeat field(txp[13]) +// DW33 +#define WF_TX_DESCRIPTOR_TXP14_DW 33 +#define WF_TX_DESCRIPTOR_TXP14_ADDR 132 +#define WF_TX_DESCRIPTOR_TXP14_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP14_SHIFT 0 +// DW34 +// DO NOT process repeat field(txp[14]) +#define WF_TX_DESCRIPTOR_TXP15_DW 34 +#define WF_TX_DESCRIPTOR_TXP15_ADDR 136 +#define WF_TX_DESCRIPTOR_TXP15_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP15_SHIFT 16 +// DW35 +// DO NOT process repeat field(txp[15]) +// DW36 +#define WF_TX_DESCRIPTOR_TXP16_DW 36 +#define WF_TX_DESCRIPTOR_TXP16_ADDR 144 +#define WF_TX_DESCRIPTOR_TXP16_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP16_SHIFT 0 +// DW37 +// DO NOT process repeat field(txp[16]) +#define WF_TX_DESCRIPTOR_TXP17_DW 37 +#define WF_TX_DESCRIPTOR_TXP17_ADDR 148 +#define WF_TX_DESCRIPTOR_TXP17_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP17_SHIFT 16 +// DW38 +// DO NOT process repeat field(txp[17]) +// DW39 +#define WF_TX_DESCRIPTOR_TXP18_DW 39 +#define WF_TX_DESCRIPTOR_TXP18_ADDR 156 +#define WF_TX_DESCRIPTOR_TXP18_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP18_SHIFT 0 +// DW40 +// DO NOT process repeat field(txp[18]) +#define WF_TX_DESCRIPTOR_TXP19_DW 40 +#define WF_TX_DESCRIPTOR_TXP19_ADDR 160 +#define WF_TX_DESCRIPTOR_TXP19_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP19_SHIFT 16 +// DW41 +// DO NOT process repeat field(txp[19]) +// DW42 +#define WF_TX_DESCRIPTOR_TXP20_DW 42 +#define WF_TX_DESCRIPTOR_TXP20_ADDR 168 +#define WF_TX_DESCRIPTOR_TXP20_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP20_SHIFT 0 +// DW43 +// DO NOT process repeat field(txp[20]) +#define WF_TX_DESCRIPTOR_TXP21_DW 43 +#define WF_TX_DESCRIPTOR_TXP21_ADDR 172 +#define WF_TX_DESCRIPTOR_TXP21_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP21_SHIFT 16 +// DW44 +// DO NOT process repeat field(txp[21]) +// DW45 +#define WF_TX_DESCRIPTOR_TXP22_DW 45 +#define WF_TX_DESCRIPTOR_TXP22_ADDR 180 +#define WF_TX_DESCRIPTOR_TXP22_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP22_SHIFT 0 +// DW46 +// DO NOT process repeat field(txp[22]) +#define WF_TX_DESCRIPTOR_TXP23_DW 46 +#define WF_TX_DESCRIPTOR_TXP23_ADDR 184 +#define WF_TX_DESCRIPTOR_TXP23_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP23_SHIFT 16 +// DW47 +// DO NOT process repeat field(txp[23]) +// DW48 +#define WF_TX_DESCRIPTOR_TXP24_DW 48 +#define WF_TX_DESCRIPTOR_TXP24_ADDR 192 +#define WF_TX_DESCRIPTOR_TXP24_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP24_SHIFT 0 +// DW49 +// DO NOT process repeat field(txp[24]) +#define WF_TX_DESCRIPTOR_TXP25_DW 49 +#define WF_TX_DESCRIPTOR_TXP25_ADDR 196 +#define WF_TX_DESCRIPTOR_TXP25_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP25_SHIFT 16 +// DW50 +// DO NOT process repeat field(txp[25]) +// DW51 +#define WF_TX_DESCRIPTOR_TXP26_DW 51 +#define WF_TX_DESCRIPTOR_TXP26_ADDR 204 +#define WF_TX_DESCRIPTOR_TXP26_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP26_SHIFT 0 +// DW52 +// DO NOT process repeat field(txp[26]) +#define WF_TX_DESCRIPTOR_TXP27_DW 52 +#define WF_TX_DESCRIPTOR_TXP27_ADDR 208 +#define WF_TX_DESCRIPTOR_TXP27_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP27_SHIFT 16 +// DW53 +// DO NOT process repeat field(txp[27]) +// DW54 +#define WF_TX_DESCRIPTOR_TXP28_DW 54 +#define WF_TX_DESCRIPTOR_TXP28_ADDR 216 +#define WF_TX_DESCRIPTOR_TXP28_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP28_SHIFT 0 +// DW55 +// DO NOT process repeat field(txp[28]) +#define WF_TX_DESCRIPTOR_TXP29_DW 55 +#define WF_TX_DESCRIPTOR_TXP29_ADDR 220 +#define WF_TX_DESCRIPTOR_TXP29_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP29_SHIFT 16 +// DW56 +// DO NOT process repeat field(txp[29]) +// DW57 +#define WF_TX_DESCRIPTOR_TXP30_DW 57 +#define WF_TX_DESCRIPTOR_TXP30_ADDR 228 +#define WF_TX_DESCRIPTOR_TXP30_MASK 0xffffffff // 31- 0 +#define WF_TX_DESCRIPTOR_TXP30_SHIFT 0 +// DW58 +// DO NOT process repeat field(txp[30]) +#define WF_TX_DESCRIPTOR_TXP31_DW 58 +#define WF_TX_DESCRIPTOR_TXP31_ADDR 232 +#define WF_TX_DESCRIPTOR_TXP31_MASK 0xffff0000 // 31-16 +#define WF_TX_DESCRIPTOR_TXP31_SHIFT 16 +// DW59 +// DO NOT process repeat field(txp[31]) + +/* TXP PAO */ +#define HIF_TXP_V2_SIZE (24 * 4) +/* DW0 */ +#define HIF_TXD_VERSION_SHIFT 19 +#define HIF_TXD_VERSION_MASK 0x00780000 + +/* DW8 */ +#define HIF_TXP_PRIORITY_SHIFT 0 +#define HIF_TXP_PRIORITY_MASK 0x00000001 +#define HIF_TXP_FIXED_RATE_SHIFT 1 +#define HIF_TXP_FIXED_RATE_MASK 0x00000002 +#define HIF_TXP_TCP_SHIFT 2 +#define HIF_TXP_TCP_MASK 0x00000004 +#define HIF_TXP_NON_CIPHER_SHIFT 3 +#define HIF_TXP_NON_CIPHER_MASK 0x00000008 +#define HIF_TXP_VLAN_SHIFT 4 +#define HIF_TXP_VLAN_MASK 0x00000010 +#define HIF_TXP_BC_MC_FLAG_SHIFT 5 +#define HIF_TXP_BC_MC_FLAG_MASK 0x00000060 +#define HIF_TXP_FR_HOST_SHIFT 7 +#define HIF_TXP_FR_HOST_MASK 0x00000080 +#define HIF_TXP_ETYPE_SHIFT 8 +#define HIF_TXP_ETYPE_MASK 0x00000100 +#define HIF_TXP_TXP_AMSDU_SHIFT 9 +#define HIF_TXP_TXP_AMSDU_MASK 0x00000200 +#define HIF_TXP_TXP_MC_CLONE_SHIFT 10 +#define HIF_TXP_TXP_MC_CLONE_MASK 0x00000400 +#define HIF_TXP_TOKEN_ID_SHIFT 16 +#define HIF_TXP_TOKEN_ID_MASK 0xffff0000 + +/* DW9 */ +#define HIF_TXP_BSS_IDX_SHIFT 0 +#define HIF_TXP_BSS_IDX_MASK 0x000000ff +#define HIF_TXP_USER_PRIORITY_SHIFT 8 +#define HIF_TXP_USER_PRIORITY_MASK 0x0000ff00 +#define HIF_TXP_BUF_NUM_SHIFT 16 +#define HIF_TXP_BUF_NUM_MASK 0x001f0000 +#define HIF_TXP_MSDU_CNT_SHIFT 21 +#define HIF_TXP_MSDU_CNT_MASK 0x03e00000 +#define HIF_TXP_SRC_SHIFT 26 +#define HIF_TXP_SRC_MASK 0x0c000000 + +/* DW10 */ +#define HIF_TXP_ETH_TYPE_SHIFT 0 +#define HIF_TXP_ETH_TYPE_MASK 0x0000ffff +#define HIF_TXP_WLAN_IDX_SHIFT 16 +#define HIF_TXP_WLAN_IDX_MASK 0x0fff0000 + +/* DW11 */ +#define HIF_TXP_PPE_INFO_SHIFT 0 +#define HIF_TXP_PPE_INFO_MASK 0xffffffff + +/* DW12 - DW31 */ +#define HIF_TXP_BUF_PTR0_L_SHIFT 0 +#define HIF_TXP_BUF_PTR0_L_MASK 0xffffffff +#define HIF_TXP_BUF_LEN0_SHIFT 0 +#define HIF_TXP_BUF_LEN0_MASK 0x00000fff +#define HIF_TXP_BUF_PTR0_H_SHIFT 12 +#define HIF_TXP_BUF_PTR0_H_MASK 0x0000f000 +#define HIF_TXP_BUF_LEN1_SHIFT 16 +#define HIF_TXP_BUF_LEN1_MASK 0x0fff0000 +#define HIF_TXP_BUF_PTR1_H_SHIFT 28 +#define HIF_TXP_BUF_PTR1_H_MASK 0xf0000000 +#define HIF_TXP_BUF_PTR1_L_SHIFT 0 +#define HIF_TXP_BUF_PTR1_L_MASK 0xffffffff + +/* DW31 */ +#define HIF_TXP_ML_SHIFT 16 +#define HIF_TXP_ML_MASK 0xffff0000 + +#endif + +#endif diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c index 2ab2a8a8..421ed69c 100644 --- a/mt7996/mtk_debugfs.c +++ b/mt7996/mtk_debugfs.c @@ -252,6 +252,21 @@ static int mt7996_amsdu_result_read(struct seq_file *s, void *data) seq_printf(s, "\n"); } + seq_printf(s, "PAO AMSDU num:\n"); + total_amsdu = 0; + for (i = 0; i < MT7996_TX_PAO_NUM_MAX; i++) + total_amsdu += dev->dbg.pao_nbuf[i]; + + for (i = 0; i < MT7996_TX_PAO_NUM_MAX; i++) { + seq_printf(s, "PAO AMSDU pack count of %d MSDU : 0x%x ", + i+1, dev->dbg.pao_nbuf[i]); + if (total_amsdu != 0) + seq_printf(s, "(%d%%)\n", dev->dbg.pao_nbuf[i] * 100 / total_amsdu); + else + seq_printf(s, "\n"); + } + + memset(dev->dbg.pao_nbuf, 0, sizeof(dev->dbg.pao_nbuf)); return 0; } diff --git a/mt7996/mtk_debugfs_i.c b/mt7996/mtk_debugfs_i.c new file mode 100644 index 00000000..9b73970d --- /dev/null +++ b/mt7996/mtk_debugfs_i.c @@ -0,0 +1,1669 @@ +#include +#include "mt7996.h" +#include "../mt76.h" +#include "mcu.h" +#include "mac.h" +#include "eeprom.h" +#include "mtk_debug.h" +#include "mtk_debug_i.h" +#include "mtk_mcu.h" +#include "mtk_mcu_i.h" + +#ifdef CONFIG_MTK_DEBUG + +void mt7996_packet_log_to_host(struct mt7996_dev *dev, const void *data, int len, int type, int des_len) +{ + struct bin_debug_hdr *hdr; + char *buf; + + if (len > 1500 - sizeof(*hdr)) + len = 1500 - sizeof(*hdr); + + buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL); + if (!buf) + return; + + hdr = (struct bin_debug_hdr *)buf; + hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC); + hdr->serial_id = cpu_to_le16(dev->fw_debug_seq++); + hdr->msg_type = cpu_to_le16(type); + hdr->len = cpu_to_le16(len); + hdr->des_len = cpu_to_le16(des_len); + + memcpy(buf + sizeof(*hdr), data, len); + + mt7996_debugfs_rx_log(dev, buf, sizeof(*hdr) + len); + kfree(buf); +} + +//bmac dump mac txp +void mt7996_dump_bmac_mac_txp_info(struct mt7996_dev *dev, __le32 *txp) +{ + struct mt7996_txp_token { + __le16 msdu[4]; + } *msdu; + struct mt7996_txp_ptr { + __le32 addr1; + __le32 addr_info; + __le32 addr2; + } *ptr; + int i = 0; + + for (i = 0; i < 12; i = i+2 ) { + if (i == 0 || i == 4) { + msdu = (struct mt7996_txp_token *) txp; + printk("msdu token(%d-%d)=%ld %ld %ld %ld (0x%08x-0x%08x)\n", i, i+3, + (msdu->msdu[0] & GENMASK(14, 0)), + (msdu->msdu[1] & GENMASK(14, 0)), + (msdu->msdu[2] & GENMASK(14, 0)), + (msdu->msdu[3] & GENMASK(14, 0)), *txp, *(txp+1)); + txp = txp + 2; + } + ptr = (struct mt7996_txp_ptr *) txp; + printk("ptr%02d : addr(0x%08x) len(%ld) addr_h(%02lx) SRC(%d) ML(%d) \n", + i, ptr->addr1, + FIELD_GET(GENMASK(11, 0), ptr->addr_info), + FIELD_GET(GENMASK(13, 12), ptr->addr_info), + !!(ptr->addr_info & BIT(14)), + !!(ptr->addr_info & BIT(15))); + printk("ptr%02d : addr(0x%08x) len(%ld) addr_h(%02lx) SRC(%d) ML(%d) \n", + i+1, ptr->addr2, + FIELD_GET(GENMASK(27, 16), ptr->addr_info), + FIELD_GET(GENMASK(29, 28), ptr->addr_info), + !!(ptr->addr_info & BIT(30)), + !!(ptr->addr_info & BIT(31))); + txp = txp + 3; + } +} + +//bmac dump hif txp +void mt7996_dump_bmac_hif_txp_info(struct mt7996_dev *dev, __le32 *txp, u32 hif_txp_ver) +{ + int i, j = 0; + u32 dw; + + printk("txp raw data: size=%d\n", HIF_TXP_V2_SIZE); + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txp, HIF_TXP_V2_SIZE, false); + + printk("BMAC_TXP Fields:\n"); + + /* dw0 */ + if (hif_txp_ver == 2) { + dw = le32_to_cpu(txp[0]); + printk("HIF_TXP_PRIORITY = %d\n", + GET_FIELD(HIF_TXP_PRIORITY, dw)); + printk("HIF_TXP_FIXED_RATE = %d\n", + GET_FIELD(HIF_TXP_FIXED_RATE, dw)); + printk("HIF_TXP_TCP = %d\n", + GET_FIELD(HIF_TXP_TCP, dw)); + printk("HIF_TXP_NON_CIPHER = %d\n", + GET_FIELD(HIF_TXP_NON_CIPHER, dw)); + printk("HIF_TXP_VLAN = %d\n", + GET_FIELD(HIF_TXP_VLAN, dw)); + printk("HIF_TXP_BC_MC_FLAG = %d\n", + GET_FIELD(HIF_TXP_BC_MC_FLAG, dw)); + printk("HIF_TXP_FR_HOST = %d\n", + GET_FIELD(HIF_TXP_FR_HOST, dw)); + printk("HIF_TXP_ETYPE = %d\n", + GET_FIELD(HIF_TXP_ETYPE, dw)); + printk("HIF_TXP_TXP_AMSDU = %d\n", + GET_FIELD(HIF_TXP_TXP_AMSDU, dw)); + printk("HIF_TXP_TXP_MC_CLONE = %d\n", + GET_FIELD(HIF_TXP_TXP_MC_CLONE, dw)); + printk("HIF_TXP_TOKEN_ID = %d\n", + GET_FIELD(HIF_TXP_TOKEN_ID, dw)); + + /* dw1 */ + dw = le32_to_cpu(txp[1]); + printk("HIF_TXP_BSS_IDX = %d\n", + GET_FIELD(HIF_TXP_BSS_IDX, dw)); + printk("HIF_TXP_USER_PRIORITY = %d\n", + GET_FIELD(HIF_TXP_USER_PRIORITY, dw)); + printk("HIF_TXP_BUF_NUM = %d\n", + GET_FIELD(HIF_TXP_BUF_NUM, dw)); + printk("HIF_TXP_MSDU_CNT = %d\n", + GET_FIELD(HIF_TXP_MSDU_CNT, dw)); + printk("HIF_TXP_SRC = %d\n", + GET_FIELD(HIF_TXP_SRC, dw)); + + /* dw2 */ + dw = le32_to_cpu(txp[2]); + printk("HIF_TXP_ETH_TYPE(network-endian) = 0x%x\n", + GET_FIELD(HIF_TXP_ETH_TYPE, dw)); + printk("HIF_TXP_WLAN_IDX = %d\n", + GET_FIELD(HIF_TXP_WLAN_IDX, dw)); + + /* dw3 */ + dw = le32_to_cpu(txp[3]); + printk("HIF_TXP_PPE_INFO = 0x%x\n", + GET_FIELD(HIF_TXP_PPE_INFO, dw)); + + for (i = 0; i < 13; i++) { + if (i % 2 == 0) { + printk("HIF_TXP_BUF_PTR%d_L = 0x%x\n", + i, GET_FIELD(HIF_TXP_BUF_PTR0_L, + le32_to_cpu(txp[4 + j]))); + j++; + printk("HIF_TXP_BUF_LEN%d = %d\n", + i, GET_FIELD(HIF_TXP_BUF_LEN0, le32_to_cpu(txp[4 + j]))); + printk("HIF_TXP_BUF_PTR%d_H = 0x%x\n", + i, GET_FIELD(HIF_TXP_BUF_PTR0_H, le32_to_cpu(txp[4 + j]))); + if (i <= 10) { + printk("HIF_TXP_BUF_LEN%d = %d\n", + i + 1, GET_FIELD(HIF_TXP_BUF_LEN1, le32_to_cpu(txp[4 + j]))); + printk("HIF_TXP_BUF_PTR%d_H = 0x%x\n", + i + 1, GET_FIELD(HIF_TXP_BUF_PTR1_H, le32_to_cpu(txp[4 + j]))); + } + j++; + } else { + printk("HIF_TXP_BUF_PTR%d_L = 0x%x\n", + i, GET_FIELD(HIF_TXP_BUF_PTR1_L, + le32_to_cpu(txp[4 + j]))); + j++; + } + } + + printk("ml = 0x%x\n", + GET_FIELD(HIF_TXP_ML, le32_to_cpu(txp[23]))); + } else { + struct mt76_connac_txp_common *txp_v1 = (struct mt76_connac_txp_common *)txp; + + printk("FLAGS = (%04x)\n", txp_v1->fw.flags); + + printk("MSDU = %d\n", txp_v1->fw.token); + + printk("BSS_IDX = %d\n", txp_v1->fw.bss_idx); + + printk("WCID = %d\n",txp_v1->fw.rept_wds_wcid); + + printk("MSDU_CNT = %d\n", txp_v1->fw.nbuf); + + for (i = 0; i < MT_TXP_MAX_BUF_NUM; i++) + printk("ptr%02d : addr(0x%08x) len(%d)\n", i, le32_to_cpu(txp_v1->fw.buf[i]), + le16_to_cpu(txp_v1->fw.len[i])); + } + +} + +/* bmac txd dump */ +void mt7996_dump_bmac_txd_info(struct mt7996_dev *dev, __le32 *txd, bool is_hif_txd, bool dump_txp) +{ + u32 hif_txp_ver = 0; + + /* dump stop */ + if (!dev->dbg.txd_read_cnt) + return; + + /* force dump */ + if (dev->dbg.txd_read_cnt > 8) + dev->dbg.txd_read_cnt = 8; + + /* dump txd_read_cnt times */ + if (dev->dbg.txd_read_cnt != 8) + dev->dbg.txd_read_cnt--; + + printk("txd raw data: size=%d\n", MT_TXD_SIZE); + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txd, MT_TXD_SIZE, false); + + printk("BMAC_TXD Fields:\n"); + /* dw0 */ + if (is_hif_txd) { + hif_txp_ver = FIELD_GET(GENMASK(22, 19), txd[0]); + printk("HIF TXD VER = %d\n", hif_txp_ver); + } + printk("TX_BYTE_COUNT = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TX_BYTE_COUNT, txd[0])); + printk("ETHER_TYPE_OFFSET(word) = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET, txd[0])); + printk("PKT_FT = %d%s%s%s%s\n", + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]), + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 0 ? "(ct)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 1 ? "(s&f)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 2 ? "(cmd)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 3 ? "(redirect)" : ""); + printk("Q_IDX = %d%s%s%s\n", + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]), + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x10 ? "(ALTX)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x11 ? "(BMC)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x12 ? "(BCN)" : ""); + + /* dw1 */ + printk("MLD_ID = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_MLD_ID, txd[1])); + printk("TGID = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TGID, txd[1])); + printk("HF = %d%s%s%s%s\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]), + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? "(eth/802.3)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 1 ? "(cmd)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? "(802.11)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? "(802.11 enhanced" : ""); + printk("802.11 HEADER_LENGTH = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? + GET_FIELD(WF_TX_DESCRIPTOR_HEADER_LENGTH, txd[1]) : 0); + printk("MRD = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? + GET_FIELD(WF_TX_DESCRIPTOR_MRD, txd[1]) : 0); + printk("EOSP = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? + GET_FIELD(WF_TX_DESCRIPTOR_EOSP, txd[1]) : 0); + printk("AMS = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? + GET_FIELD(WF_TX_DESCRIPTOR_AMS, txd[1]) : 0); + printk("RMVL = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? + GET_FIELD(WF_TX_DESCRIPTOR_RMVL, txd[1]): 0); + printk("VLAN = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? + GET_FIELD(WF_TX_DESCRIPTOR_VLAN, txd[1]) : 0); + printk("ETYP = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? + GET_FIELD(WF_TX_DESCRIPTOR_ETYP, txd[1]) : 0); + printk("TID_MGMT_TYPE = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TID_MGMT_TYPE, txd[1])); + printk("OM = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_OM, txd[1])); + printk("FR = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_FR, txd[1])); + + /* dw2 */ + printk("SUBTYPE = %d%s%s%s%s\n", + GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]), + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0) && + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 13) ? + "(action)" : "", + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1) && + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 8) ? + "(bar)" : "", + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) && + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 4) ? + "(null)" : "", + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) && + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 12) ? + "(qos null)" : ""); + + printk("FTYPE = %d%s%s%s\n", + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]), + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0 ? "(mgmt)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1 ? "(ctl)" : "", + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2 ? "(data)" : ""); + printk("BF_TYPE = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_BF_TYPE, txd[2])); + printk("OM_MAP = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_OM_MAP, txd[2])); + printk("RTS = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_RTS, txd[2])); + printk("HEADER_PADDING = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HEADER_PADDING, txd[2])); + printk("DU = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_DU, txd[2])); + printk("HE = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HE, txd[2])); + printk("FRAG = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_FRAG, txd[2])); + printk("REMAINING_TX_TIME = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_TIME, txd[2])); + printk("POWER_OFFSET = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_POWER_OFFSET, txd[2])); + + /* dw3 */ + printk("NA = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_NA, txd[3])); + printk("PF = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_PF, txd[3])); + printk("EMRD = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_EMRD, txd[3])); + printk("EEOSP = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_EEOSP, txd[3])); + printk("BM = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_BM, txd[3])); + printk("HW_AMSDU_CAP = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HW_AMSDU_CAP, txd[3])); + printk("TX_COUNT = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TX_COUNT, txd[3])); + printk("REMAINING_TX_COUNT = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_COUNT, txd[3])); + printk("SN = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_SN, txd[3])); + printk("BA_DIS = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_BA_DIS, txd[3])); + printk("PM = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_PM, txd[3])); + printk("PN_VLD = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_PN_VLD, txd[3])); + printk("SN_VLD = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_SN_VLD, txd[3])); + + /* dw4 */ + printk("PN_31_0 = 0x%x\n", + GET_FIELD(WF_TX_DESCRIPTOR_PN_31_0_, txd[4])); + + /* dw5 */ + printk("PID = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_PID, txd[5])); + printk("TXSFM = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TXSFM, txd[5])); + printk("TXS2M = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TXS2M, txd[5])); + printk("TXS2H = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TXS2H, txd[5])); + printk("FBCZ = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_FBCZ, txd[5])); + printk("BYPASS_RBB = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_BYPASS_RBB, txd[5])); + + printk("FL = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_FL, txd[5])); + printk("PN_47_32 = 0x%x\n", + GET_FIELD(WF_TX_DESCRIPTOR_PN_47_32_, txd[5])); + + /* dw6 */ + printk("AMSDU_CAP_UTXB = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB, txd[6])); + printk("DAS = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_DAS, txd[6])); + printk("DIS_MAT = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_DIS_MAT, txd[6])); + printk("MSDU_COUNT = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_MSDU_COUNT, txd[6])); + printk("TIMESTAMP_OFFSET = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX, txd[6])); + printk("FIXED_RATE_IDX = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_FIXED_RATE_IDX, txd[6])); + printk("BW = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_BW, txd[6])); + printk("VTA = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_VTA, txd[6])); + printk("SRC = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_SRC, txd[6])); + + /* dw7 */ + printk("SW_TX_TIME(unit:65536ns) = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_SW_TX_TIME , txd[7])); + printk("UT = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_UT, txd[7])); + printk("CTXD_CNT = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_CTXD_CNT, txd[7])); + printk("HM = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_HM, txd[7])); + printk("DP = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_DP, txd[7])); + printk("IP = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_IP, txd[7])); + printk("TXD_LEN = %d\n", + GET_FIELD(WF_TX_DESCRIPTOR_TXD_LEN, txd[7])); + + if (dump_txp) { + __le32 *txp = txd + 8; + + if (is_hif_txd) + mt7996_dump_bmac_hif_txp_info(dev, txp, hif_txp_ver); + else + mt7996_dump_bmac_mac_txp_info(dev, txp); + } +} + +static void +mt7996_dump_mac_fid(struct mt7996_dev *dev, u32 fid, bool is_ple) +{ +#define PLE_MEM_SIZE 128 +#define PSE_MEM_SIZE 256 + u8 data[PSE_MEM_SIZE] = {0}; + u32 addr = 0; + int i = 0, cr_cnt = PSE_MEM_SIZE; + u32 *ptr = (u32 *) data; + + if (is_ple) { + cr_cnt = PLE_MEM_SIZE; + pr_info("dump ple: fid = 0x%08x\n", fid); + } else { + pr_info("dump pse: fid = 0x%08x\n", fid); + } + + for (i = 0; i < cr_cnt; i = i + 4) { + if (is_ple) + addr = (0xa << 28 | fid << 15) + i; + else + addr = (0xb << 28 | fid << 15) + i; + *ptr = mt76_rr(dev, addr); + ptr++; + } + + printk("raw data: size=%d\n", cr_cnt); + + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)data, cr_cnt, false); + /* dump one txd info */ + if (is_ple) { + dev->dbg.txd_read_cnt = 1; + mt7996_dump_bmac_txd_info(dev, (__le32 *)&data[0], false, true); + } +} + +static int +mt7996_ple_fid_read(struct seq_file *s, void *data) { + struct mt7996_dev *dev = dev_get_drvdata(s->private); + + mt7996_dump_mac_fid(dev, dev->dbg.fid_idx, true); + return 0; +} + +static int +mt7996_pse_fid_read(struct seq_file *s, void *data) { + struct mt7996_dev *dev = dev_get_drvdata(s->private); + + mt7996_dump_mac_fid(dev, dev->dbg.fid_idx, false); + return 0; +} + +void mt7996_dump_bmac_rxd_info(struct mt7996_dev *dev, __le32 *rxd) +{ + /* dump stop */ + if (!dev->dbg.rxd_read_cnt) + return; + + /* force dump */ + if (dev->dbg.rxd_read_cnt > 8) + dev->dbg.rxd_read_cnt = 8; + + /* dump txd_read_cnt times */ + if (dev->dbg.rxd_read_cnt != 8) + dev->dbg.rxd_read_cnt--; + + printk("rxd raw data: size=%d\n", MT_TXD_SIZE); + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)rxd, 96, false); + + printk("BMAC_RXD Fields:\n"); + + /* group0 */ + /* dw0 */ + printk("RX_BYTE_COUNT = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_RX_BYTE_COUNT, le32_to_cpu(rxd[0]))); + printk("PACKET_TYPE = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_PACKET_TYPE, le32_to_cpu(rxd[0]))); + + /* dw1 */ + printk("MLD_ID = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_MLD_ID, le32_to_cpu(rxd[1]))); + printk("GROUP_VLD = 0x%x%s%s%s%s%s\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])), + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_1 ? "[group1]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_2 ? "[group2]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_3 ? "[group3]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? "[group4]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_5 ? "[group5]" : ""); + printk("KID = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_KID, le32_to_cpu(rxd[1]))); + printk("CM = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_CM, le32_to_cpu(rxd[1]))); + printk("CLM = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_CLM, le32_to_cpu(rxd[1]))); + printk("I = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_I, le32_to_cpu(rxd[1]))); + printk("T = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_T, le32_to_cpu(rxd[1]))); + printk("BN = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_BN, le32_to_cpu(rxd[1]))); + printk("BIPN_FAIL = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_BIPN_FAIL, le32_to_cpu(rxd[1]))); + + /* dw2 */ + printk("BSSID = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_BSSID, le32_to_cpu(rxd[2]))); + printk("H = %d%s\n", + GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])), + GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])) == 0 ? + "802.11 frame" : "eth/802.3 frame"); + printk("HEADER_LENGTH(word) = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_HEADER_LENGTH, le32_to_cpu(rxd[2]))); + printk("HO(word) = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_HO, le32_to_cpu(rxd[2]))); + printk("SEC_MODE = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_SEC_MODE, le32_to_cpu(rxd[2]))); + printk("MUBAR = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_MUBAR, le32_to_cpu(rxd[2]))); + printk("SWBIT = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_SWBIT, le32_to_cpu(rxd[2]))); + printk("DAF = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_DAF, le32_to_cpu(rxd[2]))); + printk("EL = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_EL, le32_to_cpu(rxd[2]))); + printk("HTF = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_HTF, le32_to_cpu(rxd[2]))); + printk("INTF = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_INTF, le32_to_cpu(rxd[2]))); + printk("FRAG = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_FRAG, le32_to_cpu(rxd[2]))); + printk("NUL = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_NUL, le32_to_cpu(rxd[2]))); + printk("NDATA = %d%s\n", + GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])), + GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])) == 0 ? + "[data frame]" : "[mgmt/ctl frame]"); + printk("NAMP = %d%s\n", + GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])), + GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])) == 0 ? + "[ampdu frame]" : "[mpdu frame]"); + printk("BF_RPT = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_BF_RPT, le32_to_cpu(rxd[2]))); + + /* dw3 */ + printk("RXV_SN = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_RXV_SN, le32_to_cpu(rxd[3]))); + printk("CH_FREQUENCY = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_CH_FREQUENCY, le32_to_cpu(rxd[3]))); + printk("A1_TYPE = %d%s%s%s%s\n", + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])), + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 0 ? + "[reserved]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 1 ? + "[uc2me]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 2 ? + "[mc]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 3 ? + "[bc]" : ""); + printk("HTC = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_HTC, le32_to_cpu(rxd[3]))); + printk("TCL = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_TCL, le32_to_cpu(rxd[3]))); + printk("BBM = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_BBM, le32_to_cpu(rxd[3]))); + printk("BU = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_BU, le32_to_cpu(rxd[3]))); + printk("CO_ANT = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_CO_ANT, le32_to_cpu(rxd[3]))); + printk("BF_CQI = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_BF_CQI, le32_to_cpu(rxd[3]))); + printk("FC = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_FC, le32_to_cpu(rxd[3]))); + printk("VLAN = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_VLAN, le32_to_cpu(rxd[3]))); + + /* dw4 */ + printk("PF = %d%s%s%s%s\n", + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])), + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 0 ? + "[msdu]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 1 ? + "[final amsdu]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 2 ? + "[middle amsdu]" : "", + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 3 ? + "[first amsdu]" : ""); + printk("MAC = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_MAC, le32_to_cpu(rxd[4]))); + printk("TID = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_TID, le32_to_cpu(rxd[4]))); + printk("ETHER_TYPE_OFFSET = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET, le32_to_cpu(rxd[4]))); + printk("IP = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_IP, le32_to_cpu(rxd[4]))); + printk("UT = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_UT, le32_to_cpu(rxd[4]))); + printk("PSE_FID = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_PSE_FID, le32_to_cpu(rxd[4]))); + + /* group4 */ + /* dw0 */ + printk("FRAME_CONTROL_FIELD = 0x%x\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? + GET_FIELD(WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD, le32_to_cpu(rxd[8])) : 0); + printk("PEER_MLD_ADDRESS_15_0 = 0x%x\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? + GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0_, + le32_to_cpu(rxd[8])) : 0); + + /* dw1 */ + printk("PEER_MLD_ADDRESS_47_16 = 0x%x\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? + GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16_, + le32_to_cpu(rxd[9])) : 0); + + /* dw2 */ + printk("FRAGMENT_NUMBER = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? + GET_FIELD(WF_RX_DESCRIPTOR_FRAGMENT_NUMBER, + le32_to_cpu(rxd[10])) : 0); + printk("SEQUENCE_NUMBER = %d\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? + GET_FIELD(WF_RX_DESCRIPTOR_SEQUENCE_NUMBER, + le32_to_cpu(rxd[10])) : 0); + printk("QOS_CONTROL_FIELD = 0x%x\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? + GET_FIELD(WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD, + le32_to_cpu(rxd[10])) : 0); + + /* dw3 */ + printk("HT_CONTROL_FIELD = 0x%x\n", + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) + & BMAC_GROUP_VLD_4 ? + GET_FIELD(WF_RX_DESCRIPTOR_HT_CONTROL_FIELD, + le32_to_cpu(rxd[11])) : 0); +} + +static int mt7996_token_read(struct seq_file *s, void *data) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + int id, count = 0; + struct mt76_txwi_cache *txwi; + + seq_printf(s, "Cut through token:\n"); + spin_lock_bh(&dev->mt76.token_lock); + idr_for_each_entry(&dev->mt76.token, txwi, id) { + seq_printf(s, "%4d ", id); + count++; + if (count % 8 == 0) + seq_printf(s, "\n"); + } + spin_unlock_bh(&dev->mt76.token_lock); + seq_printf(s, "\n"); + + return 0; +} + +static int mt7996_token_txd_read(struct seq_file *s, void *data) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + struct mt76_txwi_cache *t; + u8* txwi; + + printk("\n"); + spin_lock_bh(&dev->mt76.token_lock); + + t = idr_find(&dev->mt76.token, dev->dbg.token_idx); + + spin_unlock_bh(&dev->mt76.token_lock); + if (t != NULL) { + struct mt76_dev *mdev = &dev->mt76; + txwi = ((u8*)(t)) - (mdev->drv->txwi_size); + /* dump one txd info */ + dev->dbg.txd_read_cnt = 1; + mt7996_dump_bmac_txd_info(dev, (__le32 *)txwi, true, true); + printk("\n"); + printk("[SKB]\n"); + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false); + printk("\n"); + } + return 0; +} + +static int mt7996_rx_token_read(struct seq_file *s, void *data) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + int id, count = 0; + struct mt76_rxwi_cache *r; + + seq_printf(s, "Rx cut through token:\n"); + spin_lock_bh(&dev->mt76.rx_token_lock); + idr_for_each_entry(&dev->mt76.rx_token, r, id) { + count++; + } + seq_printf(s, "\ttotal:%8d used:%8d\n", + dev->mt76.rx_token_size, count); + spin_unlock_bh(&dev->mt76.rx_token_lock); + + return 0; +} + +static int mt7996_rx_msdu_pg_read(struct seq_file *s, void *data) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + struct mt7996_rro_cfg *rro = &dev->rro; + struct list_head *p; + int i, count = 0, total = 0; + + seq_printf(s, "Rx Msdu page:\n"); + spin_lock(&rro->lock); + for (i = 0; i < MT7996_RRO_MSDU_PG_HASH_SIZE; i++) { + list_for_each(p, &rro->pg_hash_head[i]) { + count++; + } + } + + total = count; + list_for_each(p, &rro->pg_addr_cache) { + total++; + } + seq_printf(s, "\ttotal:%8d used:%8d\n", total, count); + spin_unlock(&rro->lock); + + return 0; +} + +/* AMSDU SETTING */ +static ssize_t mt7996_amsdu_algo_write(struct file *file, + const char __user *user_buf, + size_t count, + loff_t *ppos) +{ + struct mt7996_dev *dev = file->private_data; + char buf[100]; + int ret; + struct { + u8 _rsv[4]; + + u16 tag; + u16 len; + + u16 wlan_idx; + u8 algo_en; + u8 rsv[1]; + } __packed data = { + .tag = cpu_to_le16(UNI_MEC_AMSDU_ALGO_EN_STA), + .len = cpu_to_le16(sizeof(data) - 4), + }; + + if (count >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, user_buf, count)) + return -EFAULT; + + if (count && buf[count - 1] == '\n') + buf[count - 1] = '\0'; + else + buf[count] = '\0'; + + if (sscanf(buf, "%hu %hhu", &data.wlan_idx, &data.algo_en) != 2) + return -EINVAL; + + if (data.wlan_idx >= mt7996_wtbl_size(dev)) + return -EINVAL; + + ret = mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(MEC), &data, + sizeof(data), true); + if (ret) + return -EINVAL; + + return count; +} +static const struct file_operations fops_amsdu_algo = { + .write = mt7996_amsdu_algo_write, + .read = NULL, + .open = simple_open, + .llseek = default_llseek, +}; + +static ssize_t mt7996_amsdu_para_write(struct file *file, + const char __user *user_buf, + size_t count, + loff_t *ppos) +{ + struct mt7996_dev *dev = file->private_data; + char buf[100]; + int ret; + struct { + u8 _rsv[4]; + + u16 tag; + u16 len; + + u16 wlan_idx; + u8 amsdu_en; + u8 num; + u16 lenth; + u8 rsv[2]; + } __packed data = { + .tag = cpu_to_le16(UNI_MEC_AMSDU_PARA_STA), + .len = cpu_to_le16(sizeof(data) - 4), + }; + + if (count >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, user_buf, count)) + return -EFAULT; + + if (count && buf[count - 1] == '\n') + buf[count - 1] = '\0'; + else + buf[count] = '\0'; + + if (sscanf(buf, "%hu %hhu %hhu %hu", &data.wlan_idx, &data.amsdu_en, &data.num, &data.lenth) != 4) + return -EINVAL; + + if (data.wlan_idx >= mt7996_wtbl_size(dev)) + return -EINVAL; + + ret = mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(MEC), &data, + sizeof(data), true); + if (ret) + return -EINVAL; + + return count; +} +static const struct file_operations fops_amsdu_para = { + .write = mt7996_amsdu_para_write, + .read = NULL, + .open = simple_open, + .llseek = default_llseek, +}; + +/* PSE INFO */ +static struct bmac_queue_info_t pse_queue_empty_info[] = { + {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0}, + {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1}, + {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2}, + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3}, + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */ + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, + {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */ + {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0}, + {"MDP TX Q0", ENUM_UMAC_LMAC_PORT_2, 1}, + {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2}, + {"SEC TX Q0", ENUM_UMAC_LMAC_PORT_2, 3}, + {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4}, + {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5}, + {"MDP_TXIOC Q0", ENUM_UMAC_LMAC_PORT_2, 6}, + {"MDP_RXIOC Q0", ENUM_UMAC_LMAC_PORT_2, 7}, + {"MDP TX Q1", ENUM_UMAC_LMAC_PORT_2, 0x11}, + {"SEC TX Q1", ENUM_UMAC_LMAC_PORT_2, 0x13}, + {"MDP_TXIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x16}, + {"MDP_RXIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x17}, + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, 4}, + {NULL, 0, 0}, {NULL, 0, 0}, + {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F} +}; + +static struct bmac_queue_info_t pse_queue_empty2_info[] = { + {"MDP_TDPIOC Q0", ENUM_UMAC_LMAC_PORT_2, 0x8}, + {"MDP_RDPIOC Q0", ENUM_UMAC_LMAC_PORT_2, 0x9}, + {"MDP_TDPIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x18}, + {"MDP_RDPIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x19}, + {"MDP_TDPIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x28}, + {"MDP_RDPIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x29}, + {NULL, 0, 0}, + {"MDP_RDPIOC Q3", ENUM_UMAC_LMAC_PORT_2, 0x39}, + {"MDP TX Q2", ENUM_UMAC_LMAC_PORT_2, 0x21}, + {"SEC TX Q2", ENUM_UMAC_LMAC_PORT_2, 0x23}, + {"MDP_TXIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x26}, + {"MDP_RXIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x27}, + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, + {"MDP_RXIOC Q3", ENUM_UMAC_LMAC_PORT_2, 0x37}, + {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, + {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1}, + {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2}, + {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3}, + {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4}, + {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5}, + {"HIF Q6", ENUM_UMAC_HIF_PORT_0, 6}, + {"HIF Q7", ENUM_UMAC_HIF_PORT_0, 7}, + {"HIF Q8", ENUM_UMAC_HIF_PORT_0, 8}, + {"HIF Q9", ENUM_UMAC_HIF_PORT_0, 9}, + {"HIF Q10", ENUM_UMAC_HIF_PORT_0, 10}, + {"HIF Q11", ENUM_UMAC_HIF_PORT_0, 11}, + {"HIF Q12", ENUM_UMAC_HIF_PORT_0, 12}, + {"HIF Q13", ENUM_UMAC_HIF_PORT_0, 13}, + {NULL, 0, 0}, {NULL, 0, 0} +}; + +static int +mt7996_pseinfo_read(struct seq_file *s, void *data) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + u32 pse_buf_ctrl, pg_sz, pg_num; + u32 pse_stat[2], pg_flow_ctrl[28] = {0}; + u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail; + u32 max_q, min_q, rsv_pg, used_pg; + int i; + + pse_buf_ctrl = mt76_rr(dev, WF_PSE_TOP_PBUF_CTRL_ADDR); + pse_stat[0] = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR); + pse_stat[1] = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_1_ADDR); + pg_flow_ctrl[0] = mt76_rr(dev, WF_PSE_TOP_FREEPG_CNT_ADDR); + pg_flow_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR); + pg_flow_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_PG_HIF0_GROUP_ADDR); + pg_flow_ctrl[3] = mt76_rr(dev, WF_PSE_TOP_HIF0_PG_INFO_ADDR); + pg_flow_ctrl[4] = mt76_rr(dev, WF_PSE_TOP_PG_HIF1_GROUP_ADDR); + pg_flow_ctrl[5] = mt76_rr(dev, WF_PSE_TOP_HIF1_PG_INFO_ADDR); + pg_flow_ctrl[6] = mt76_rr(dev, WF_PSE_TOP_PG_CPU_GROUP_ADDR); + pg_flow_ctrl[7] = mt76_rr(dev, WF_PSE_TOP_CPU_PG_INFO_ADDR); + pg_flow_ctrl[8] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC0_GROUP_ADDR); + pg_flow_ctrl[9] = mt76_rr(dev, WF_PSE_TOP_LMAC0_PG_INFO_ADDR); + pg_flow_ctrl[10] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC1_GROUP_ADDR); + pg_flow_ctrl[11] = mt76_rr(dev, WF_PSE_TOP_LMAC1_PG_INFO_ADDR); + pg_flow_ctrl[12] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC2_GROUP_ADDR); + pg_flow_ctrl[13] = mt76_rr(dev, WF_PSE_TOP_LMAC2_PG_INFO_ADDR); + pg_flow_ctrl[14] = mt76_rr(dev, WF_PSE_TOP_PG_PLE_GROUP_ADDR); + pg_flow_ctrl[15] = mt76_rr(dev, WF_PSE_TOP_PLE_PG_INFO_ADDR); + pg_flow_ctrl[16] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC3_GROUP_ADDR); + pg_flow_ctrl[17] = mt76_rr(dev, WF_PSE_TOP_LMAC3_PG_INFO_ADDR); + pg_flow_ctrl[18] = mt76_rr(dev, WF_PSE_TOP_PG_MDP_GROUP_ADDR); + pg_flow_ctrl[19] = mt76_rr(dev, WF_PSE_TOP_MDP_PG_INFO_ADDR); + pg_flow_ctrl[20] = mt76_rr(dev, WF_PSE_TOP_PG_PLE1_GROUP_ADDR); + pg_flow_ctrl[21] = mt76_rr(dev, WF_PSE_TOP_PLE1_PG_INFO_ADDR); + pg_flow_ctrl[22] = mt76_rr(dev, WF_PSE_TOP_PG_MDP2_GROUP_ADDR); + pg_flow_ctrl[23] = mt76_rr(dev, WF_PSE_TOP_MDP2_PG_INFO_ADDR); + pg_flow_ctrl[24] = mt76_rr(dev, WF_PSE_TOP_PG_MDP3_GROUP_ADDR); + pg_flow_ctrl[25] = mt76_rr(dev, WF_PSE_TOP_MDP3_PG_INFO_ADDR); + pg_flow_ctrl[26] = mt76_rr(dev, WF_PSE_TOP_PG_HIF2_GROUP_ADDR); + pg_flow_ctrl[27] = mt76_rr(dev, WF_PSE_TOP_HIF2_PG_INFO_ADDR); + /* Configuration Info */ + printk("PSE Configuration Info:\n"); + printk("\tPacket Buffer Control: 0x%08x\n", pse_buf_ctrl); + pg_sz = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT; + printk("\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128)); + printk("\t\tPage Offset=%d(in unit of 64KB)\n", + (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT); + pg_num = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT; + printk("\t\tTotal page numbers=%d pages\n", pg_num); + /* Page Flow Control */ + printk("PSE Page Flow Control:\n"); + printk("\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]); + fpg_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT; + printk("\t\tThe toal page number of free=0x%03x\n", fpg_cnt); + ffa_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT; + printk("\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt); + printk("\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]); + fpg_head = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT; + fpg_tail = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT; + printk("\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head); + printk("\tReserved page counter of HIF0 group: 0x%08x\n", pg_flow_ctrl[2]); + printk("\tHIF0 group page status: 0x%08x\n", pg_flow_ctrl[3]); + min_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of HIF1 group: 0x%08x\n", pg_flow_ctrl[4]); + printk("\tHIF1 group page status: 0x%08x\n", pg_flow_ctrl[5]); + min_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of HIF2 group: 0x%08x\n", pg_flow_ctrl[26]); + printk("\tHIF2 group page status: 0x%08x\n", pg_flow_ctrl[27]); + min_q = (pg_flow_ctrl[26] & WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[26] & WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of HIF2 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[27] & WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_MASK) >> WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[27] & WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_MASK) >> WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of HIF2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of CPU group: 0x%08x\n", pg_flow_ctrl[6]); + printk("\tCPU group page status: 0x%08x\n", pg_flow_ctrl[7]); + min_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of LMAC0 group: 0x%08x\n", pg_flow_ctrl[8]); + printk("\tLMAC0 group page status: 0x%08x\n", pg_flow_ctrl[9]); + min_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of LMAC1 group: 0x%08x\n", pg_flow_ctrl[10]); + printk("\tLMAC1 group page status: 0x%08x\n", pg_flow_ctrl[11]); + min_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of LMAC2 group: 0x%08x\n", pg_flow_ctrl[11]); + printk("\tLMAC2 group page status: 0x%08x\n", pg_flow_ctrl[12]); + min_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + + printk("\tReserved page counter of LMAC3 group: 0x%08x\n", pg_flow_ctrl[16]); + printk("\tLMAC3 group page status: 0x%08x\n", pg_flow_ctrl[17]); + min_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + + printk("\tReserved page counter of PLE group: 0x%08x\n", pg_flow_ctrl[14]); + printk("\tPLE group page status: 0x%08x\n", pg_flow_ctrl[15]); + min_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg); + + printk("\tReserved page counter of PLE1 group: 0x%08x\n", pg_flow_ctrl[14]); + printk("\tPLE1 group page status: 0x%08x\n", pg_flow_ctrl[15]); + min_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + + printk("\tReserved page counter of MDP group: 0x%08x\n", pg_flow_ctrl[18]); + printk("\tMDP group page status: 0x%08x\n", pg_flow_ctrl[19]); + min_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of MDP2 group: 0x%08x\n", pg_flow_ctrl[22]); + printk("\tMDP2 group page status: 0x%08x\n", pg_flow_ctrl[23]); + min_q = (pg_flow_ctrl[22] & WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[22] & WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of MDP2 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[23] & WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_MASK) >> WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[23] & WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_MASK) >> WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of MDP2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + printk("\tReserved page counter of MDP3 group: 0x%08x\n", pg_flow_ctrl[24]); + printk("\tMDP3 group page status: 0x%08x\n", pg_flow_ctrl[25]); + min_q = (pg_flow_ctrl[24] & WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_SHFT; + max_q = (pg_flow_ctrl[24] & WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of MDP3 group=0x%03x/0x%03x\n", max_q, min_q); + rsv_pg = (pg_flow_ctrl[25] & WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_MASK) >> WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_SHFT; + used_pg = (pg_flow_ctrl[25] & WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_MASK) >> WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of MDP3 group=0x%03x/0x%03x\n", used_pg, rsv_pg); + /* Queue Empty Status */ + printk("PSE Queue Empty Status:\n"); + printk("\tQUEUE_EMPTY: 0x%08x, QUEUE_EMPTY2: 0x%08x\n", pse_stat[0], pse_stat[1]); + printk("\t\tCPU Q0/1/2/3/4 empty=%d/%d/%d/%d/%d\n", + (pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT, + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_SHFT)); + printk("\t\tHIF Q0/1/2/3/4/5/6/7/8/9/10/11/12/13 empty=%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d\n", + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_SHFT)); + printk("\t\tLMAC TX Q empty=%d\n", + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT)); + printk("\t\tMDP TX Q0/Q1/Q2/RX Q empty=%d/%d/%d/%d\n", + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT)); + printk("\t\tSEC TX Q0/Q1/Q2/RX Q empty=%d/%d/%d/%d\n", + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT)); + printk("\t\tSFD PARK Q empty=%d\n", + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT)); + printk("\t\tMDP TXIOC Q0/Q1/Q2 empty=%d/%d/%d\n", + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_SHFT)); + printk("\t\tMDP RXIOC Q0/Q1/Q2/Q3 empty=%d/%d/%d/%d\n", + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT), + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_SHFT), + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_SHFT)); + printk("\t\tRLS Q empty=%d\n", + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT)); + printk("Nonempty Q info:\n"); + + for (i = 0; i < 31; i++) { + if (((pse_stat[0] & (0x1 << i)) >> i) == 0) { + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; + + if (pse_queue_empty_info[i].QueueName != NULL) { + printk("\t%s: ", pse_queue_empty_info[i].QueueName); + fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[1] |= (pse_queue_empty_info[i].Portid << WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); + fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + } else + continue; + + fl_que_ctrl[0] |= (0x1 << 31); + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR); + fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR); + hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; + tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; + pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", + tfid, hfid, pktcnt); + } + } + + for (i = 0; i < 31; i++) { + if (((pse_stat[1] & (0x1 << i)) >> i) == 0) { + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; + + if (pse_queue_empty2_info[i].QueueName != NULL) { + printk("\t%s: ", pse_queue_empty2_info[i].QueueName); + fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[1] |= (pse_queue_empty2_info[i].Portid << WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); + fl_que_ctrl[0] |= (pse_queue_empty2_info[i].Queueid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + } else + continue; + + fl_que_ctrl[0] |= (0x1 << 31); + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR); + fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR); + hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; + tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; + pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", + tfid, hfid, pktcnt); + } + } + + return true; +} + +/* PLE INFO */ +static char *sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"}; +static struct bmac_queue_info ple_queue_empty_info[] = { + {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0, 0}, + {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1, 0}, + {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2, 0}, + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3, 0}, + {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x10, 0}, + {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, 0x11, 0}, + {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, 0x12, 0}, + {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, 0x13, 0}, + {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x10, 1}, + {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, 0x11, 1}, + {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, 0x12, 1}, + {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, 0x13, 1}, + {"ALTX Q2", ENUM_UMAC_LMAC_PORT_2, 0x10, 2}, + {"BMC Q2", ENUM_UMAC_LMAC_PORT_2, 0x11, 2}, + {"BCN Q2", ENUM_UMAC_LMAC_PORT_2, 0x12, 2}, + {"PSMP Q2", ENUM_UMAC_LMAC_PORT_2, 0x13, 2}, + {"NAF Q", ENUM_UMAC_LMAC_PORT_2, 0x18, 0}, + {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, 0x19, 0}, + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, /* 18, 19 not defined */ + {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a, 0}, + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, + {"RLS4 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7c, 0}, + {"RLS3 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7d, 0}, + {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e, 0}, + {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f, 0} +}; + +static struct bmac_queue_info_t ple_txcmd_queue_empty_info[] = { + {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40}, + {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41}, + {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42}, + {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43}, + {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44}, + {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45}, + {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46}, + {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47}, + {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48}, + {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49}, + {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a}, + {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b}, + {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c}, + {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d}, + {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e}, + {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f}, + {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50}, + {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51}, + {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52}, + {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53}, + {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54}, + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, +}; + +static void +mt7996_get_ple_acq_stat(struct mt7996_dev *dev, u32 *ple_stat) +{ + ple_stat[0] = mt76_rr(dev, WF_PLE_TOP_QUEUE_EMPTY_ADDR); + + ple_stat[1] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR); + ple_stat[2] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR); + ple_stat[3] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR); + ple_stat[4] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR); + ple_stat[5] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR); + ple_stat[6] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR); + ple_stat[7] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR); + ple_stat[8] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR); + ple_stat[9] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR); + + ple_stat[10] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR); + ple_stat[11] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR); + ple_stat[12] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR); + ple_stat[13] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR); + ple_stat[14] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR); + ple_stat[15] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR); + ple_stat[16] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR); + ple_stat[17] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR); + ple_stat[18] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR); + + ple_stat[19] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR); + ple_stat[20] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR); + ple_stat[21] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR); + ple_stat[22] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR); + ple_stat[23] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR); + ple_stat[24] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR); + ple_stat[25] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR); + ple_stat[26] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR); + ple_stat[27] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR); + + ple_stat[28] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR); + ple_stat[29] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR); + ple_stat[30] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR); + ple_stat[31] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR); + ple_stat[32] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR); + ple_stat[33] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR); + ple_stat[34] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR); + ple_stat[35] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR); + ple_stat[36] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR); +} + +static void +mt7996_get_ple_txcmd_stat(struct mt7996_dev *dev, u32 *ple_txcmd_stat) +{ + *ple_txcmd_stat = mt76_rr(dev, WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR); +} + +static void +mt7996_get_dis_sta_map(struct mt7996_dev *dev, u32 *dis_sta_map) +{ + /* Todo: check these CRs */ +#if 0 + dis_sta_map[0] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP0_ADDR); + dis_sta_map[1] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP1_ADDR); + dis_sta_map[2] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP2_ADDR); + dis_sta_map[3] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP3_ADDR); + dis_sta_map[4] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP4_ADDR); + dis_sta_map[5] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP5_ADDR); + dis_sta_map[6] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP6_ADDR); + dis_sta_map[7] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP7_ADDR); + dis_sta_map[8] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP8_ADDR); +#endif +} + +static void +mt7996_get_sta_pause(struct mt7996_dev *dev, u32 *sta_pause) +{ + /* BELLWETHER TODO: Wait MIB counter API implement complete */ +} + +static int +mt7996_show_sta_acq_info(struct seq_file *s, u32 *ple_stat, + u32 *sta_pause, u32 *dis_sta_map, + u32 dumptxd) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + int i, j; + u32 total_nonempty_cnt = 0; + + for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) { /* show AC Q info */ + for (i = 0; i < 32; i++) { + if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) { + u32 hfid, tfid, pktcnt, ac_num = j / CR_NUM_OF_AC, ctrl = 0; + u32 sta_num = i + (j % CR_NUM_OF_AC) * 32, fl_que_ctrl[3] = {0}; + u32 wmmidx = 0; + struct mt7996_sta *msta; + struct mt76_wcid *wcid; + struct ieee80211_sta *sta = NULL; + + wcid = rcu_dereference(dev->mt76.wcid[sta_num]); + sta = wcid_to_sta(wcid); + if (!sta) { + printk("ERROR!! no found STA wcid=%d\n", sta_num); + return 0; + } + msta = container_of(wcid, struct mt7996_sta, wcid); + wmmidx = msta->vif->mt76.wmm_idx; + + printk("\tSTA%d AC%d: ", sta_num, ac_num); + + if (is_mt7996(&dev->mt76)) { + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[1] |= (ENUM_UMAC_LMAC_PORT_2 << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); + fl_que_ctrl[0] |= (ac_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + fl_que_ctrl[0] |= (sta_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT); + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + } else { + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT); + fl_que_ctrl[0] |= (ac_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + fl_que_ctrl[0] |= (sta_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT); + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + + } + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> + WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x", + tfid, hfid, pktcnt); + + if (((sta_pause[j % CR_NUM_OF_AC] & 0x1 << i) >> i) == 1) + ctrl = 2; + + if (((dis_sta_map[j % CR_NUM_OF_AC] & 0x1 << i) >> i) == 1) + ctrl = 1; + + printk(" ctrl = %s", sta_ctrl_reg[ctrl]); + printk(" (wmmidx=%d)\n", wmmidx); + + total_nonempty_cnt++; + + if (pktcnt > 0 && dumptxd > 0) + mt7996_dump_mac_fid(dev, hfid, true); + } + } + } + + return total_nonempty_cnt; +} + +static void +mt7996_show_txcmdq_info(struct seq_file *s, u32 ple_txcmd_stat) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + int i; + + printk("Nonempty TXCMD Q info:\n"); + for (i = 0; i < 32 ; i++) { + if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) { + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; + + if (ple_txcmd_queue_empty_info[i].QueueName != NULL) { + printk("\t%s: ", ple_txcmd_queue_empty_info[i].QueueName); + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid << + WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT); + fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid << + WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + } else + continue; + + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> + WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", + tfid, hfid, pktcnt); + } + } +} + +static int +mt7996_pleinfo_read(struct seq_file *s, void *data) +{ + struct mt7996_dev *dev = dev_get_drvdata(s->private); + u32 ple_buf_ctrl, pg_sz, pg_num; + u32 ple_stat[ALL_CR_NUM_OF_ALL_AC + 1] = {0}, pg_flow_ctrl[10] = {0}; + u32 ple_native_txcmd_stat; + u32 ple_txcmd_stat; + u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0}; + u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q; + u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu; + int i, j; + u32 dumptxd = dev->dbg.dump_ple_txd; + + ple_buf_ctrl = mt76_rr(dev, WF_PLE_TOP_PBUF_CTRL_ADDR); + mt7996_get_ple_acq_stat(dev, ple_stat); + ple_txcmd_stat = mt76_rr(dev, WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR); + mt7996_get_ple_txcmd_stat(dev, &ple_native_txcmd_stat); + pg_flow_ctrl[0] = mt76_rr(dev, WF_PLE_TOP_FREEPG_CNT_ADDR); + pg_flow_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR); + pg_flow_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_GROUP_ADDR); + pg_flow_ctrl[3] = mt76_rr(dev, WF_PLE_TOP_HIF_PG_INFO_ADDR); + pg_flow_ctrl[4] = mt76_rr(dev, WF_PLE_TOP_PG_CPU_GROUP_ADDR); + pg_flow_ctrl[5] = mt76_rr(dev, WF_PLE_TOP_CPU_PG_INFO_ADDR); + pg_flow_ctrl[6] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR); + pg_flow_ctrl[7] = mt76_rr(dev, WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR); + pg_flow_ctrl[8] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR); + pg_flow_ctrl[9] = mt76_rr(dev, WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR); + mt7996_get_dis_sta_map(dev, dis_sta_map); + mt7996_get_sta_pause(dev, sta_pause); + + /* Configuration Info */ + printk("PLE Configuration Info:\n"); + printk("\tPacket Buffer Control(0x82060014): 0x%08x\n", ple_buf_ctrl); + pg_sz = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT; + printk("\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 128 : 64)); + printk("\t\tPage Offset=%d(in unit of 2KB)\n", + (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT); + pg_num = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT; + printk("\t\tTotal Page=%d pages\n", pg_num); + + /* Page Flow Control */ + printk("PLE Page Flow Control:\n"); + printk("\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]); + fpg_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT; + printk("\t\tThe toal page number of free=0x%03x\n", fpg_cnt); + ffa_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT; + printk("\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt); + printk("\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]); + fpg_head = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT; + fpg_tail = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT; + printk("\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head); + printk("\tReserved page counter of HIF group: 0x%08x\n", pg_flow_ctrl[2]); + printk("\tHIF group page status: 0x%08x\n", pg_flow_ctrl[3]); + hif_min_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT; + hif_max_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q); + rpg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT; + upg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif); + + printk("\tReserved page counter of WMTXD group: 0x%08x\n", pg_flow_ctrl[8]); + printk("\tWMTXD group page status: 0x%08x\n", pg_flow_ctrl[9]); + cpu_min_q = (pg_flow_ctrl[8] & WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_SHFT; + cpu_max_q = (pg_flow_ctrl[8] & WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of WMTXD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); + rpg_cpu = (pg_flow_ctrl[9] & WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_SHFT; + upg_cpu = (pg_flow_ctrl[9] & WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of WMTXD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); + + printk("\tReserved page counter of HIF_TXCMD group: 0x%08x\n", pg_flow_ctrl[6]); + printk("\tHIF_TXCMD group page status: 0x%08x\n", pg_flow_ctrl[7]); + cpu_min_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT; + cpu_max_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); + rpg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT; + upg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); + + printk("\tReserved page counter of CPU group(0x820c0150): 0x%08x\n", pg_flow_ctrl[4]); + printk("\tCPU group page status(0x820c0154): 0x%08x\n", pg_flow_ctrl[5]); + cpu_min_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT; + cpu_max_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT; + printk("\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); + rpg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT; + upg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT; + printk("\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); + + if ((ple_stat[0] & WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK) == 0) { + for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) { + if (j % CR_NUM_OF_AC == 0) { + printk("\n\tNonempty AC%d Q of STA#: ", j / CR_NUM_OF_AC); + } + + for (i = 0; i < 32; i++) { + if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) { + printk("%d ", i + (j % CR_NUM_OF_AC) * 32); + } + } + } + + printk("\n"); + } + + printk("non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat); + + printk("Nonempty Q info:\n"); + + if (is_mt7996(&dev->mt76)) + goto mt7996; + + for (i = 0; i < 32; i++) { + if (((ple_stat[0] & (0x1 << i)) >> i) == 0) { + u32 hfid, tfid, pktcnt, waitcnt = 3, fl_que_ctrl[3] = {0}; + + if (ple_queue_empty_info[i].QueueName != NULL) { + printk("\t%s: ", ple_queue_empty_info[i].QueueName); + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[1] |= (ple_queue_empty_info[i].Portid << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); + fl_que_ctrl[1] |= (ple_queue_empty_info[i].tgid << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_SHFT); + /* Bellwether HW issue, Queueid need + (4 * band_idx) */ + fl_que_ctrl[0] |= ((ple_queue_empty_info[i].Queueid + 4 * ple_queue_empty_info[i].tgid) + << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + } else + continue; + + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + + do { + /* Polling if HW done (0 = Done, 1 = Not done) */ + fl_que_ctrl[0] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR); + fl_que_ctrl[0] &= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + waitcnt -= 1; + } while (fl_que_ctrl[0] && waitcnt); + + if (fl_que_ctrl[0] && waitcnt == 0) { + printk("Polling HW too many times, drop information\n"); + continue; + } + + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", + tfid, hfid, pktcnt); + + if (pktcnt > 0 && dumptxd > 0) + mt7996_dump_mac_fid(dev, hfid, true); + } + } + + goto out; +mt7996: + for (i = 0; i < 32; i++) { + if (((ple_stat[0] & (0x1 << i)) >> i) == 0) { + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; + + if (ple_queue_empty_info[i].QueueName != NULL) { + printk("\t%s: ", ple_queue_empty_info[i].QueueName); + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT); + fl_que_ctrl[0] |= (ple_queue_empty_info[i].tgid << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_TGID_SHFT); + /* Bellwether HW issue, Queueid need + (4 * band_idx) */ + fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + } else + continue; + + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); + + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", + tfid, hfid, pktcnt); + + if (pktcnt > 0 && dumptxd > 0) + mt7996_dump_mac_fid(dev, hfid, true); + } + } + +out: + mt7996_show_sta_acq_info(s, ple_stat, sta_pause, dis_sta_map, dumptxd); + mt7996_show_txcmdq_info(s, ple_native_txcmd_stat); + + return true; +} + +/* DRR */ +static int +mt7996_drr_info(struct seq_file *s, void *data) +{ + /* BELLWETHER TODO: Wait MIB counter API implement complete */ + return 0; +} + +int mt7996_mtk_init_debugfs_internal(struct mt7996_phy *phy, struct dentry *dir) +{ + struct mt7996_dev *dev = phy->dev; + + mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0); + + debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir, + mt7996_drr_info); + + debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir, + mt7996_pleinfo_read); + + debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir, + mt7996_pseinfo_read); + + debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx); + debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir, + mt7996_token_read); + debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir, + mt7996_token_txd_read); + debugfs_create_u32("txd_dump", 0600, dir, &dev->dbg.txd_read_cnt); + debugfs_create_u32("rxd_dump", 0600, dir, &dev->dbg.rxd_read_cnt); + debugfs_create_devm_seqfile(dev->mt76.dev, "rx_token", dir, + mt7996_rx_token_read); + debugfs_create_devm_seqfile(dev->mt76.dev, "rx_msdu_pg", dir, + mt7996_rx_msdu_pg_read); + /* ple/pse fid raw data dump */ + debugfs_create_u32("fid_idx", 0600, dir, &dev->dbg.fid_idx); + debugfs_create_devm_seqfile(dev->mt76.dev, "ple_fid", dir, + mt7996_ple_fid_read); + debugfs_create_devm_seqfile(dev->mt76.dev, "pse_fid", dir, + mt7996_pse_fid_read); + /* amsdu */ + debugfs_create_file("amsdu_algo", 0600, dir, dev, &fops_amsdu_algo); + debugfs_create_file("amsdu_para", 0600, dir, dev, &fops_amsdu_para); + + debugfs_create_u8("dump_ple_txd", 0600, dir, &dev->dbg.dump_ple_txd); + return 0; +} + +#endif diff --git a/mt7996/mtk_mcu_i.c b/mt7996/mtk_mcu_i.c new file mode 100644 index 00000000..64badf5d --- /dev/null +++ b/mt7996/mtk_mcu_i.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: ISC +/* + * Copyright (C) 2023 MediaTek Inc. + */ + +#include +#include +#include "mt7996.h" +#include "mcu.h" +#include "mac.h" +#include "mtk_mcu.h" +#include "mtk_mcu_i.h" + +#ifdef CONFIG_MTK_DEBUG + + +#endif diff --git a/mt7996/mtk_mcu_i.h b/mt7996/mtk_mcu_i.h new file mode 100644 index 00000000..38a007d2 --- /dev/null +++ b/mt7996/mtk_mcu_i.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: ISC */ +/* + * Copyright (C) 2023 MediaTek Inc. + */ + +#ifndef __MT7996_MTK_MCU_I_H +#define __MT7996_MTK_MCU_I_H + +#include "../mt76_connac_mcu.h" + +#ifdef CONFIG_MTK_DEBUG + + +#endif + +#endif -- 2.39.2